M-Labs/vexriscv-rust
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  • 6008a2dc04 lib: support feature llvm_asm master occheung 2021-07-08 16:43:36 +0800
  • c5fbc0cc82 asm: use llvm_asm! macro() Sean Cross 2020-08-04 17:18:10 +0800
  • ba269ff348
         Merge pull request #3 from Disasm/deduplicate Sean Cross 2020-06-14 22:33:16 +0800
  • 81c5f3d619
         Update README Vadim Kaushan 2020-06-14 15:00:27 +0300
  • ca21628edb
         Fix badges in README Vadim Kaushan 2020-06-14 14:58:03 +0300
  • 9a9d9121b4
         Regenerate binaries Vadim Kaushan 2020-06-14 14:53:56 +0300
  • 496120e89f
         Add debug info, strip prefix Vadim Kaushan 2020-06-14 14:53:38 +0300
  • e21ce5249f
         Remove write functions for read-only registers Vadim Kaushan 2020-06-14 14:40:51 +0300
  • 707f51f46e
         Fix docs Vadim Kaushan 2020-06-14 14:39:24 +0300
  • 426fc067b4
         Allow unused macros Vadim Kaushan 2020-06-14 14:33:44 +0300
  • 7ce847ee3c
         Fix register docs Vadim Kaushan 2020-06-14 14:32:33 +0300
  • a131c16360
         Remove unused dependencies Vadim Kaushan 2020-06-14 14:22:50 +0300
  • a9b4b7149f
         Regenerate binaries Vadim Kaushan 2020-06-14 14:22:08 +0300
  • 11e7118729
         Remove all the RISC-V standard registers Vadim Kaushan 2020-06-14 14:20:38 +0300
  • b4546d1827
         Remove asm and interrupt modules Vadim Kaushan 2020-06-14 14:17:55 +0300
  • 9bf5caafc2
         Remove #![deny(warnings)] (anti-pattern) Vadim Kaushan 2020-06-14 14:16:26 +0300
  • 18995feba8
         Revert "README: Obsolete" Vadim Kaushan 2020-06-14 14:06:04 +0300
  • b7befcf608
         README: Obsolete Sean Cross 2020-03-18 23:36:30 +0800
  • 5846f57ab1 cargo: bump version to 0.0.2 v0.0.2 Sean Cross 2020-01-08 17:23:05 +0800
  • fd54453416 register: add vexriscv-specific registers Sean Cross 2020-01-08 17:22:16 +0800
  • 8bc0b06f95 bin: update name of object file Sean Cross 2019-12-28 18:29:06 +0800
  • 5121f28fde cargo: remove vexriscv category v0.0.1 Sean Cross 2019-12-28 18:14:52 +0800
  • 28ded4136a vexriscv: clone from riscv crate Sean Cross 2019-12-28 18:11:12 +0800
  • 0259333c75
         Merge #34 bors[bot] 2019-10-10 07:32:26 +0000
  • 7a9aa062a0 Allow writing directly to satp register Gui Andrade 2019-10-08 18:10:38 -0700
  • 95c52341c4 mip: Add set/clear functions for bits Gui Andrade 2019-10-08 17:56:39 -0700
  • 0eda3c511c
         Merge #32 bors[bot] 2019-09-13 21:15:02 +0000
  • 73f45e3dbf
         Merge branch 'master' into ustatus Ales Katona 2019-09-13 11:21:44 -0600
  • 9d68612325
         Merge #33 bors[bot] 2019-09-13 01:06:16 +0000
  • b834ae45a5
         Do not use bare-metal v0.2.5 (changes MSRV) Vadim Kaushan 2019-09-05 19:53:02 +0300
  • 8840aee369
         ucause only as readable bits Ales Katona 2019-08-31 17:32:43 -0600
  • e1232ed680
         clean up formatting Ales Katona 2019-08-31 16:12:39 -0600
  • cdf6a33665
         remove XS and FS from ustatus Ales Katona 2019-08-31 16:10:56 -0600
  • 13831f7a80
         revert scause specific trap/exceptions Ales Katona 2019-08-31 16:09:47 -0600
  • f443bcf698
         remove invalid comment Ales Katona 2019-08-28 09:26:02 -0600
  • 30555e4d79
         fix typos in asm calls Ales Katona 2019-08-27 09:47:57 -0600
  • 49446ad869
         fix ustatus doc typos Ales Katona 2019-08-27 09:46:14 -0600
  • 2180ef44d5
         add user trap setup and handling registers Ales Katona 2019-08-27 09:40:47 -0600
  • 4094a32f43 Merge #30 bors[bot] 2019-07-27 12:59:37 +0000
  • b53e0a5cd2 add riscv32i target Sebastien Bourdeauducq 2019-07-26 00:13:38 +0800
  • 7f1e4a56cf Merge #31 bors[bot] 2019-07-23 17:41:40 +0000
  • d3dc245ce4
         Bump version (0.5.4) Vadim Kaushan 2019-07-03 01:37:34 +0300
  • 31f4127702
         Add PMP CSRs Vadim Kaushan 2019-06-26 11:25:45 +0300
  • f37ab221c8
         Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs Vadim Kaushan 2019-06-26 00:51:37 +0300
  • 298a8b6f6e
         Provide write() for mepc Vadim Kaushan 2019-06-25 23:48:47 +0300
  • 7a8d3d1f6c
         Implement mscratch and mtval registers Vadim Kaushan 2019-06-25 23:48:27 +0300
  • 00367d4fd2
         Add sections to the registers module Vadim Kaushan 2019-06-25 23:31:06 +0300
  • 370a654d2c
         Regenerate binaries Vadim Kaushan 2019-06-25 23:12:18 +0300
  • a659a0cc39
         Declare all the CSR registers in asm.S Vadim Kaushan 2019-06-25 23:11:58 +0300
  • ac2ac6756b
         Derive useful traits for enums Vadim Kaushan 2019-06-25 23:02:45 +0300
  • 5a1ab837b4 Merge #28 bors[bot] 2019-06-25 19:40:12 +0000
  • 2965734b7b
         Bump version (0.5.3) Vadim Kaushan 2019-04-29 10:45:19 +0200
  • 2ef11206bd
         Regenerate binaries Vadim Kaushan 2019-04-29 10:44:45 +0200
  • cf9008492a
         Add marchid, mhartid and mimpid registers Vadim Kaushan 2019-04-29 10:43:51 +0200
  • 1e514648fd Merge #26 bors[bot] 2019-04-01 19:06:47 +0000
  • c3ff23989e
         Bump version (0.5.2) Vadim Kaushan 2019-04-01 19:59:10 +0300
  • ca797a35d8
         Fix Misa::has_extension() Vadim Kaushan 2019-04-01 19:58:40 +0300
  • 33070435a0 Merge #25 bors[bot] 2019-03-28 21:20:43 +0000
  • 6425cab701 Merge #24 bors[bot] 2019-03-28 20:47:36 +0000
  • c1a3fe2dd9 Rename RISCV to RISC-V mara 2019-03-28 17:53:14 +0100
  • 6bfccad567
         Bump version (0.5.1) Vadim Kaushan 2019-03-28 19:06:40 +0300
  • 7112ef8af2
         Regenerate blobs Vadim Kaushan 2019-03-28 18:57:28 +0300
  • 5baba0cb32
         Add write function for sstatus register Vadim Kaushan 2019-03-28 18:56:49 +0300
  • 9bb3b5803c
         Refactoring: use set_bits() in set_fs function Vadim Kaushan 2019-03-28 17:59:07 +0300
  • 5ef90e3189
         Fix set_spp and set_mpp functions Vadim Kaushan 2019-03-28 17:42:38 +0300
  • 6a2bdbf38d
         Refactoring Vadim Kaushan 2019-03-18 18:25:16 +0300
  • 4fb81f4860
         Add FS and XS fields of mstatus Vadim Kaushan 2019-03-18 18:08:14 +0300
  • 32eba6c1ea Merge #23 bors[bot] 2019-03-17 18:47:24 +0000
  • 8222812d8d
         Regenerate blobs Vadim Kaushan 2019-03-17 19:06:48 +0300
  • 4ad2150a24
         Add fcsr register Vadim Kaushan 2019-03-17 19:06:29 +0300
  • 037e8bdcf4 Merge #22 bors[bot] 2019-03-17 14:47:55 +0000
  • 7d4919a67c
         Add MSRV policy Vadim Kaushan 2019-03-17 17:29:48 +0300
  • 799cdaf6d2
         Fix docs Vadim Kaushan 2019-03-17 17:28:05 +0300
  • 698cb306ea
         Enable gcc caching Vadim Kaushan 2019-03-17 16:57:16 +0300
  • 87453e6b0a
         Change PATH in CI script Vadim Kaushan 2019-03-17 16:52:15 +0300
  • a8040bd24b
         Check blobs in separate target Vadim Kaushan 2019-03-17 16:45:28 +0300
  • 9352831150
         Simplify CI scripts Vadim Kaushan 2019-03-17 16:30:23 +0300
  • 41b4c1c1e6
         Remove useless 'set' commands Vadim Kaushan 2019-03-17 16:28:53 +0300
  • 662dcb67d2
         Update Travis build matrix Vadim Kaushan 2019-03-17 16:27:41 +0300
  • 2450868523 Merge #21 bors[bot] 2019-03-01 15:40:36 +0000
  • a091d236dd Bump version Vadim Kaushan 2019-03-01 17:48:59 +0300
  • 925c496949 Read composite CSRs as one 64-bit value Vadim Kaushan 2019-03-01 17:41:41 +0300
  • b665adeb95 Refactoring: use get_bit() instead of shifts Vadim Kaushan 2019-03-01 17:10:45 +0300
  • ab15a6a8c7 CI: check new targets Vadim Kaushan 2019-03-01 17:02:13 +0300
  • 427c3b9035 Generate binaries for 64-bit targets Vadim Kaushan 2019-03-01 17:00:36 +0300
  • 70bdf2f2f7 Merge #20 bors[bot] 2019-02-19 20:31:01 +0000
  • 8cbb3878e5
         move doc comments inside macro invocations Andy Russell 2019-02-19 13:45:32 -0500
  • c99d70bf02 Merge #19 bors[bot] 2019-02-07 16:55:23 +0000
  • e2ed39decd Leave just team e-mail in authors Vadim Kaushan 2019-02-07 19:53:22 +0300
  • 8d6b2fe111 Add team e-mail to authors Vadim Kaushan 2019-02-06 22:17:30 +0300
  • 1ee535e94f Merge #18 bors[bot] 2019-02-06 16:03:42 +0000
  • 01cfa71fd0 remove the unused 'const-fn' feature Jorge Aparicio 2019-02-06 16:48:23 +0100
  • 4e3517aaec Merge #17 bors[bot] 2019-01-24 14:37:18 +0000
  • 6c82b0ae4c Bump version Vadim Kaushan 2019-01-24 17:20:50 +0300
  • 16fdb16730 Update docs Vadim Kaushan 2019-01-24 17:20:23 +0300
  • ac1cba597a Fix RISC-V name Vadim Kaushan 2019-01-24 17:19:32 +0300
  • d67f4acc3b Merge #16 bors[bot] 2019-01-22 22:36:46 +0000
  • 7e2103e566 Check build on stable Vadim Kaushan 2018-12-23 19:33:44 +0100
  • 02c9295587 Check binary blobs during CI Vadim Kaushan 2018-12-23 11:37:47 +0100
  • a51143d366 Implement asm functions Vadim Kaushan 2018-12-23 11:25:04 +0100