Merge branch 'master' of https://github.com/jbqubit/saymapp
commit
a83a18f807
6
pp.md
6
pp.md
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@ -254,7 +254,8 @@ Expectations for testing of all stuffed PCBs.
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- AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
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- AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
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- SDRAM PRBS write-then-read at [TODO ____ data rate]
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- SDRAM PRBS write-then-read at [TODO ____ data rate]
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- AMC backplane ethernet PRBS at 1 GSPS
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- AMC backplane ethernet PRBS at 1 GSPS
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- SFP loop-back PRBS at 1 Gb/s
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- SFP loop-back PRBS at 6 Gb/s
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- AMC backplane PRBS at 6 Gb/s
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- FMC loop-back PRBS [TODO ____ data rate]
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- FMC loop-back PRBS [TODO ____ data rate]
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- Realistic FPGA fabric load and clock activity
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- Realistic FPGA fabric load and clock activity
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- MMC configuration including power supply sequencing and IPMI
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- MMC configuration including power supply sequencing and IPMI
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@ -497,7 +498,8 @@ Adapt to be included in ARTIQ built-in self-test suite.
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- __M3.10__ DRTIO for RTM
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- __M3.10__ DRTIO for RTM
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- in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA
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- in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA
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- replace serwb with pure RTIO link
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- replace serwb with pure DRTIO link
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- perform all initialization using ARTIQ kernels: PLL chip programming, DAC chip programming, DAC synchronization, JESD core control.
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----------
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----------
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