From 3b89a16bd0c49b65f7eb0a1481cb9cce549b701b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Thu, 17 Jan 2019 11:36:50 +0800 Subject: [PATCH 1/3] replace serwb with pure DRTIO link --- pp.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pp.md b/pp.md index 3194309..3b0f690 100644 --- a/pp.md +++ b/pp.md @@ -483,7 +483,7 @@ Each MTk includes a short report and option to implement. - __M3.10__ DRTIO for RTM - in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA - - replace serwb with pure RTIO link + - replace serwb with pure DRTIO link ---------- From 4c100eded9e5a1e63e0240d49cda11c8ead0c2b4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Thu, 17 Jan 2019 11:38:23 +0800 Subject: [PATCH 2/3] Update pp.md --- pp.md | 1 + 1 file changed, 1 insertion(+) diff --git a/pp.md b/pp.md index 3b0f690..2143c18 100644 --- a/pp.md +++ b/pp.md @@ -484,6 +484,7 @@ Each MTk includes a short report and option to implement. - __M3.10__ DRTIO for RTM - in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA - replace serwb with pure DRTIO link + - perform all initialization using ARTIQ kernels: PLL chip programming, DAC chip programming, DAC synchronization, JESD core control. ---------- From 2f56e4d7bf1a71f60a6f7cbae2c814df90ec71f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Fri, 18 Jan 2019 23:20:52 +0800 Subject: [PATCH 3/3] Update pp.md --- pp.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/pp.md b/pp.md index 2143c18..dd2012f 100644 --- a/pp.md +++ b/pp.md @@ -254,7 +254,8 @@ Expectations for testing of all stuffed PCBs. - AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs - SDRAM PRBS write-then-read at [TODO ____ data rate] - AMC backplane ethernet PRBS at 1 GSPS - - SFP loop-back PRBS at 1 Gb/s + - SFP loop-back PRBS at 6 Gb/s + - AMC backplane PRBS at 6 Gb/s - FMC loop-back PRBS [TODO ____ data rate] - Realistic FPGA fabric load and clock activity - MMC configuration including power supply sequencing and IPMI