diff --git a/pp.md b/pp.md
index 395446b..7569747 100644
--- a/pp.md
+++ b/pp.md
@@ -254,7 +254,8 @@ Expectations for testing of all stuffed PCBs.
     - AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
     - SDRAM PRBS write-then-read at [TODO ____ data rate]
     - AMC backplane ethernet PRBS at 1 GSPS
-    - SFP loop-back PRBS at 1 Gb/s
+    - SFP loop-back PRBS at 6 Gb/s
+    - AMC backplane PRBS at 6 Gb/s
     - FMC loop-back PRBS [TODO ____ data rate]
     - Realistic FPGA fabric load and clock activity
 - MMC configuration including power supply sequencing and IPMI
@@ -497,7 +498,8 @@ Adapt to be included in ARTIQ built-in self-test suite.
 
 - __M3.10__ DRTIO for RTM
     - in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA
-    - replace serwb with pure RTIO link
+    - replace serwb with pure DRTIO link
+    - perform all initialization using ARTIQ kernels: PLL chip programming, DAC chip programming, DAC synchronization, JESD core control.
 
 ----------