Update pp.md

pp.md

@@ -254,7 +254,8 @@ Expectations for testing of all stuffed PCBs.
     - AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
     - SDRAM PRBS write-then-read at [TODO ____ data rate]
     - AMC backplane ethernet PRBS at 1 GSPS
-    - SFP loop-back PRBS at 1 Gb/s
+    - SFP loop-back PRBS at 6 Gb/s
+    - AMC backplane PRBS at 6 Gb/s
     - FMC loop-back PRBS [TODO ____ data rate]
     - Realistic FPGA fabric load and clock activity
 - MMC configuration including power supply sequencing and IPMI