 Sebastien Bourdeauducq
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b2fd23dadc
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increase buffer size
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2022-08-30 19:24:46 +08:00 |
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Sebastien Bourdeauducq
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800569780c
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transfer data over TCP
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2022-08-30 18:55:33 +08:00 |
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Sebastien Bourdeauducq
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13a44fc185
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dma: work around BRAM->AXI Xilinx insanity
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2022-08-30 16:41:45 +08:00 |
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Sebastien Bourdeauducq
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ec417eaf1e
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dma: fix/improve logic
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2022-08-30 16:39:35 +08:00 |
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Sebastien Bourdeauducq
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39b9563d2e
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typo
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2022-08-30 16:38:41 +08:00 |
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Sebastien Bourdeauducq
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8a93f74c70
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clock system with ADC clock
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2022-08-29 22:43:51 +08:00 |
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Sebastien Bourdeauducq
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77f727e71e
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stop driving FCLK
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2022-08-29 22:16:03 +08:00 |
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Sebastien Bourdeauducq
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bd6fccf0ea
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update firmware dependencies
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2022-08-29 20:50:01 +08:00 |
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Sebastien Bourdeauducq
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bf13e9f7c3
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ADC DMA complete, not working for obscure reason
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2020-10-25 18:58:33 +08:00 |
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Sebastien Bourdeauducq
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461c722975
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update dependencies
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2020-10-25 15:20:32 +08:00 |
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Sebastien Bourdeauducq
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2c588992c5
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DMA demo
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2020-10-25 15:16:03 +08:00 |
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Sebastien Bourdeauducq
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e628928dca
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fix logging
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2020-10-15 15:39:50 +08:00 |
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Sebastien Bourdeauducq
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42c0c16648
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infrastructure fixes
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2020-10-14 21:34:49 +08:00 |
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Sebastien Bourdeauducq
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51c4de4347
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initial commit
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2020-10-14 15:56:10 +08:00 |