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stop driving FCLK

This commit is contained in:
Sebastien Bourdeauducq 2022-08-29 22:16:03 +08:00
parent 3855b61dfb
commit 77f727e71e
1 changed files with 0 additions and 4 deletions
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4
src/gateware/rust-pitaya.py
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@ -35,10 +35,6 @@ class RustPitaya(SoCCore):
AsyncResetSynchronizer(self.cd_adc, ResetSignal()),
]
adc_pads = platform.request("adc")
self.specials += [
Instance("ODDR", o_Q=adc_pads.clk[0], i_D1=1, i_D2=0, i_CE=1, i_C=self.cd_adc.clk),
Instance("ODDR", o_Q=adc_pads.clk[1], i_D1=0, i_D2=1, i_CE=1, i_C=self.cd_adc.clk),
]
self.comb += adc_pads.cdcs.eq(1)
for port in adc_pads.data_a, adc_pads.data_b:
platform.add_platform_command("set_input_delay -max 3.400 -clock clk_adc [get_ports {port}[*]]", port=port)