stop driving FCLK
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@ -35,10 +35,6 @@ class RustPitaya(SoCCore):
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AsyncResetSynchronizer(self.cd_adc, ResetSignal()),
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]
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adc_pads = platform.request("adc")
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self.specials += [
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Instance("ODDR", o_Q=adc_pads.clk[0], i_D1=1, i_D2=0, i_CE=1, i_C=self.cd_adc.clk),
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Instance("ODDR", o_Q=adc_pads.clk[1], i_D1=0, i_D2=1, i_CE=1, i_C=self.cd_adc.clk),
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]
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self.comb += adc_pads.cdcs.eq(1)
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for port in adc_pads.data_a, adc_pads.data_b:
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platform.add_platform_command("set_input_delay -max 3.400 -clock clk_adc [get_ports {port}[*]]", port=port)
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