dma: work around BRAM->AXI Xilinx insanity

src/gateware/dma.py

@@ -1,6 +1,6 @@
 from migen import *
 from migen.genlib.fsm import FSM
-from migen.genlib.fifo import SyncFIFOBuffered
+from migen.genlib.fifo import SyncFIFO
 from migen_axi.interconnect import axi
 from misoc.interconnect.csr import *
 
@@ -69,7 +69,7 @@ class ADCWriter(Module):
         self.overflow = Signal()
         self.busy = Signal()
 
-        fifo = SyncFIFOBuffered(64, 512)
+        fifo = SyncFIFO(64, 32, fwft=True)
         self.submodules += fifo
 
         # FIFO write