M-Labs
/
rust-pitaya
2
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

typo

master
Sebastien Bourdeauducq 2022-08-30 16:38:41 +08:00
parent 8a93f74c70
commit 39b9563d2e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/gateware/rust-pitaya.py
View File

@ -22,7 +22,7 @@ class RustPitaya(SoCCore):
ident = self.__class__.__name__
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
# CLock everything from the ADC clock
# Clock everything from the ADC clock
clk125_pads = platform.request("clk125")
platform.add_platform_command("create_clock -name clk_sys -period 8 [get_ports {port}]", port=clk125_pads.p)
self.clock_domains.cd_sys = ClockDomain(reset_less=True)