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a84b6d50b8
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Add UJ-type instruction format
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2020-07-30 13:15:17 +08:00 |
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3dc2a174fd
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Refactor AUIPC instruction
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2020-07-30 13:01:13 +08:00 |
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927c12e97c
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Refactor LUI instruction
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2020-07-30 12:55:57 +08:00 |
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34c8b6cf3d
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Create U-type instruction format
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2020-07-30 12:45:32 +08:00 |
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c9c47ddc35
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Create general instruction class
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2020-07-30 12:06:51 +08:00 |
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65576d0e70
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Add rvfi_unique_check
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2020-07-29 17:05:34 +08:00 |
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b6f72ce7c9
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Add rvfi_reg_check
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2020-07-29 16:47:36 +08:00 |
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d24d466e72
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Add rvfi_pc_fwd_check
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2020-07-29 13:43:50 +08:00 |
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e0bc557d49
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Add rvfi_pc_bwd_check
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2020-07-29 13:35:21 +08:00 |
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226b225324
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Add rvfi_liveness_check
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2020-07-29 13:18:23 +08:00 |
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0aaf7e8d03
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Resolve import issue in rvfi_insn_check.py for now
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2020-07-29 12:55:36 +08:00 |
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0c971e96ce
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Update rvfi_insn_check.py
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2020-07-28 17:55:30 +08:00 |
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032e4c254d
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Create template for RVFI instruction check
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2020-07-28 14:25:14 +08:00 |
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bae6fb38bd
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Add rvfi_imem_check
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2020-07-28 14:21:51 +08:00 |
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9908c603fe
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Add rvfi_ill_check
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2020-07-28 14:04:13 +08:00 |
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26a0af8517
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Add rvfi_hang_check
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2020-07-28 13:42:38 +08:00 |
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0ae0e9c356
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Add rvfi_dmem_check
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2020-07-27 15:31:46 +08:00 |
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4ba5262165
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Add rvfi_channel check
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2020-07-27 14:37:10 +08:00 |
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8cb5110199
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Add check for causality
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2020-07-27 14:16:42 +08:00 |
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2421f1f6b6
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Add RV32IM ISA
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2020-07-24 13:51:04 +08:00 |
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5bce84836c
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Add REMU instruction for RV32M
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2020-07-24 13:32:43 +08:00 |
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4600eaeb74
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Add REM instruction for RV32M
|
2020-07-24 13:30:06 +08:00 |
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7f3f88cb69
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Add DIVU instruction for RV32M
|
2020-07-24 13:27:48 +08:00 |
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2b198303c6
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Add DIV instruction for RV32M
|
2020-07-24 13:25:17 +08:00 |
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f13208455d
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Add MULHU instruction for RV32M
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2020-07-24 13:22:41 +08:00 |
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7a61919a88
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Add MULHSU instruction for RV32M
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2020-07-24 13:20:05 +08:00 |
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9b4f6ac359
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Add MULH instruction for RV32M
|
2020-07-24 13:16:47 +08:00 |
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c72205d433
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Modify MUL instruction to use alternative operations
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2020-07-24 13:13:03 +08:00 |
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dec39cb11d
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Re-add MUL instruction
|
2020-07-24 12:55:11 +08:00 |
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f33d229b2c
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Fix XOR instruction
|
2020-07-24 12:49:33 +08:00 |
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d54269d3f0
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Fix SUB instruction
|
2020-07-24 12:48:08 +08:00 |
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fe2ff5150a
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Fix SRL instruction
|
2020-07-24 12:46:24 +08:00 |
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6d35ecdc80
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Fix SRA instruction
|
2020-07-24 12:44:44 +08:00 |
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3c1510ebbc
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Fix SLT instruction
|
2020-07-24 12:42:27 +08:00 |
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18e43d9689
|
Fix SLL instruction
|
2020-07-24 12:40:28 +08:00 |
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d59ebda628
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Fix OR instruction
|
2020-07-24 12:32:59 +08:00 |
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3028246b73
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Fix AND instruction
|
2020-07-24 12:24:43 +08:00 |
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eedfc843f7
|
Fix ADD instruction
|
2020-07-24 12:21:07 +08:00 |
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73005eb3c3
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Revert MUL instruction
|
2020-07-24 12:17:02 +08:00 |
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14c87fdde2
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Add MUL instruction for RV32M
|
2020-07-24 12:13:40 +08:00 |
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35a53071aa
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Complete generator for RV32I ISA
|
2020-07-23 14:33:25 +08:00 |
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2e7cc106aa
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Add missing return in ports in RV32I ISA
|
2020-07-23 12:57:32 +08:00 |
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badd480a45
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Prepare generator script for RV32I ISA
|
2020-07-23 12:42:59 +08:00 |
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d54a60879d
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Add list of supported instructions for RV32I
|
2020-07-23 11:18:41 +08:00 |
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41f01f22a8
|
Update README.md
|
2020-07-22 16:44:46 +08:00 |
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61393b9a4f
|
Add AND instruction for RV32I
|
2020-07-22 16:39:08 +08:00 |
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93978ccdb4
|
Add OR instruction for RV32I
|
2020-07-22 16:36:40 +08:00 |
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4eae7064fb
|
Add SRA instruction for RV32I
|
2020-07-22 16:32:51 +08:00 |
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|
ada2a09818
|
Add SRL instruction for RV32I
|
2020-07-22 16:16:27 +08:00 |
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192aec2347
|
Add XOR instruction for RV32I
|
2020-07-22 16:11:58 +08:00 |
|
