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riscv-formal-nmigen
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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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Donald Sebastian Leung 2e7cc106aa Add missing return in ports in RV32I ISA 2020-07-23 12:57:32 +08:00
insns Add missing return in ports in RV32I ISA 2020-07-23 12:57:32 +08:00
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README.md Update README.md 2020-07-22 16:44:46 +08:00

README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Dependencies

Build

TODO

Support

The full RISC-V specification is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.

License

See LICENSE