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65e4b68517
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Fix BNE instruction
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2020-07-30 16:26:29 +08:00 |
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4146a2ed20
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Fix BEQ instruction
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2020-07-30 16:24:04 +08:00 |
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9ddc5563f7
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Fix JALR instruction
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2020-07-30 16:19:01 +08:00 |
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b583ab728f
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Fix JAL instruction
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2020-07-30 16:16:06 +08:00 |
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6cff1038be
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Fix AUIPC instruction
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2020-07-30 16:12:10 +08:00 |
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4d62caadc7
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Fix U-type instruction format
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2020-07-30 16:08:24 +08:00 |
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e24ddd4269
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Fix LUI instruction
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2020-07-30 16:07:47 +08:00 |
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9974db7e7b
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Refactor BGEU instruction
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2020-07-30 15:53:39 +08:00 |
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331cfda279
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Refactor BLTU instruction
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2020-07-30 15:49:56 +08:00 |
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847099e4de
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Refactor BGE instruction
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2020-07-30 15:46:18 +08:00 |
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583d165ec1
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Refactor BLT instruction
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2020-07-30 15:42:10 +08:00 |
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31f6847640
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Refactor BNE instruction
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2020-07-30 14:14:24 +08:00 |
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3d1bb14bae
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Refactor BEQ instruction
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2020-07-30 14:10:48 +08:00 |
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4a695c950d
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Add SB-type instruction format
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2020-07-30 14:03:59 +08:00 |
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f4f5e94843
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Refactor JALR instruction
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2020-07-30 13:56:30 +08:00 |
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e6c6f0462e
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Add I-type instruction format
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2020-07-30 13:48:01 +08:00 |
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7846ba95ac
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Refactor JAL instruction
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2020-07-30 13:34:52 +08:00 |
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a84b6d50b8
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Add UJ-type instruction format
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2020-07-30 13:15:17 +08:00 |
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3dc2a174fd
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Refactor AUIPC instruction
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2020-07-30 13:01:13 +08:00 |
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927c12e97c
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Refactor LUI instruction
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2020-07-30 12:55:57 +08:00 |
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34c8b6cf3d
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Create U-type instruction format
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2020-07-30 12:45:32 +08:00 |
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c9c47ddc35
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Create general instruction class
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2020-07-30 12:06:51 +08:00 |
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2421f1f6b6
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Add RV32IM ISA
|
2020-07-24 13:51:04 +08:00 |
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5bce84836c
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Add REMU instruction for RV32M
|
2020-07-24 13:32:43 +08:00 |
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4600eaeb74
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Add REM instruction for RV32M
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2020-07-24 13:30:06 +08:00 |
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7f3f88cb69
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Add DIVU instruction for RV32M
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2020-07-24 13:27:48 +08:00 |
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2b198303c6
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Add DIV instruction for RV32M
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2020-07-24 13:25:17 +08:00 |
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f13208455d
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Add MULHU instruction for RV32M
|
2020-07-24 13:22:41 +08:00 |
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7a61919a88
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Add MULHSU instruction for RV32M
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2020-07-24 13:20:05 +08:00 |
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9b4f6ac359
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Add MULH instruction for RV32M
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2020-07-24 13:16:47 +08:00 |
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c72205d433
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Modify MUL instruction to use alternative operations
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2020-07-24 13:13:03 +08:00 |
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dec39cb11d
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Re-add MUL instruction
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2020-07-24 12:55:11 +08:00 |
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f33d229b2c
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Fix XOR instruction
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2020-07-24 12:49:33 +08:00 |
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d54269d3f0
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Fix SUB instruction
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2020-07-24 12:48:08 +08:00 |
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fe2ff5150a
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Fix SRL instruction
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2020-07-24 12:46:24 +08:00 |
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6d35ecdc80
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Fix SRA instruction
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2020-07-24 12:44:44 +08:00 |
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3c1510ebbc
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Fix SLT instruction
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2020-07-24 12:42:27 +08:00 |
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18e43d9689
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Fix SLL instruction
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2020-07-24 12:40:28 +08:00 |
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d59ebda628
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Fix OR instruction
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2020-07-24 12:32:59 +08:00 |
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3028246b73
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Fix AND instruction
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2020-07-24 12:24:43 +08:00 |
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eedfc843f7
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Fix ADD instruction
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2020-07-24 12:21:07 +08:00 |
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73005eb3c3
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Revert MUL instruction
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2020-07-24 12:17:02 +08:00 |
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14c87fdde2
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Add MUL instruction for RV32M
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2020-07-24 12:13:40 +08:00 |
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35a53071aa
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Complete generator for RV32I ISA
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2020-07-23 14:33:25 +08:00 |
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2e7cc106aa
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Add missing return in ports in RV32I ISA
|
2020-07-23 12:57:32 +08:00 |
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badd480a45
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Prepare generator script for RV32I ISA
|
2020-07-23 12:42:59 +08:00 |
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d54a60879d
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Add list of supported instructions for RV32I
|
2020-07-23 11:18:41 +08:00 |
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61393b9a4f
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Add AND instruction for RV32I
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2020-07-22 16:39:08 +08:00 |
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93978ccdb4
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Add OR instruction for RV32I
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2020-07-22 16:36:40 +08:00 |
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4eae7064fb
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Add SRA instruction for RV32I
|
2020-07-22 16:32:51 +08:00 |
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