Add missing return in ports in RV32I ISA

insns/isa_rv32i.py

@@ -45,6 +45,7 @@ class rvfi_isa_rv32i(Elaboratable):
             self.spec_mem_wmask,
             self.spec_mem_wdata
         ]
+        return input_ports + output_ports
     def elaborate(self, platform):
         m = Module()
 

insns/isa_rv32i_gen.py

@@ -48,6 +48,7 @@ with open('isa_rv32i.py', 'w') as isa_rv32i:
     fprint("            self.spec_mem_wmask,")
     fprint("            self.spec_mem_wdata")
     fprint("        ]")
+    fprint("        return input_ports + output_ports")
     fprint("    def elaborate(self, platform):")
     fprint("        m = Module()")
     fprint("")