58 lines
1.9 KiB
Python
58 lines
1.9 KiB
Python
# Generated by isa_rv32i_gen.py
|
|
from nmigen import *
|
|
|
|
class rvfi_isa_rv32i(Elaboratable):
|
|
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
|
|
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
|
|
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
|
|
self.rvfi_valid = Signal(1)
|
|
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
|
|
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
|
|
self.spec_valid = Signal(1)
|
|
self.spec_trap = Signal(1)
|
|
self.spec_rs1_addr = Signal(5)
|
|
self.spec_rs2_addr = Signal(5)
|
|
self.spec_rd_addr = Signal(5)
|
|
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
|
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
|
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
|
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
|
def ports(self):
|
|
input_ports = [
|
|
self.rvfi_valid,
|
|
self.rvfi_insn,
|
|
self.rvfi_pc_rdata,
|
|
self.rvfi_rs1_rdata,
|
|
self.rvfi_rs2_rdata,
|
|
self.rvfi_mem_rdata
|
|
]
|
|
output_ports = [
|
|
self.spec_valid,
|
|
self.spec_trap,
|
|
self.spec_rs1_addr,
|
|
self.spec_rs2_addr,
|
|
self.spec_rd_addr,
|
|
self.spec_rd_wdata,
|
|
self.spec_pc_wdata,
|
|
self.spec_mem_addr,
|
|
self.spec_mem_rmask,
|
|
self.spec_mem_wmask,
|
|
self.spec_mem_wdata
|
|
]
|
|
return input_ports + output_ports
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
|
|
return m
|
|
|
|
test = rvfi_isa_rv32i()
|
|
test.ports()
|
|
test.elaborate(platform=None)
|