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riscv-formal-nmigen
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Add missing return in ports in RV32I ISA

This commit is contained in:
Donald Sebastian Leung 2020-07-23 12:57:32 +08:00
parent badd480a45
commit 2e7cc106aa
2 changed files with 2 additions and 0 deletions
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1
insns/isa_rv32i.py
View File

@ -45,6 +45,7 @@ class rvfi_isa_rv32i(Elaboratable):
self.spec_mem_wmask, self.spec_mem_wmask,
self.spec_mem_wdata self.spec_mem_wdata
] ]
return input_ports + output_ports
def elaborate(self, platform): def elaborate(self, platform):
m = Module() m = Module()

1
insns/isa_rv32i_gen.py
View File

@ -48,6 +48,7 @@ with open('isa_rv32i.py', 'w') as isa_rv32i:
fprint(" self.spec_mem_wmask,") fprint(" self.spec_mem_wmask,")
fprint(" self.spec_mem_wdata") fprint(" self.spec_mem_wdata")
fprint(" ]") fprint(" ]")
fprint(" return input_ports + output_ports")
fprint(" def elaborate(self, platform):") fprint(" def elaborate(self, platform):")
fprint(" m = Module()") fprint(" m = Module()")
fprint("") fprint("")