Merge pull request 'Refactor supported instructions to improve code reuse' (#1) from feature/refactor-insns into master

Merging since the current state of `insns/` is a clear improvement over the previous state in terms of maintainability and code duplication, though further refactoring is required which will happen in the next pull request.

README.md

@@ -10,7 +10,7 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
 
 TODO
 
-## Support
+## Scope
 
 The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.
 

insns/README.md

@@ -0,0 +1,28 @@
+# RISC-V Instructions
+
+Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*.
+
+| Instruction type | Instructions |
+| --- | --- |
+| U-type | lui, auipc |
+| UJ-type | jal |
+| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi |
+| SB-type | beq, bne, blt, bge, bltu, bgeu |
+| S-type | sb, sh, sw |
+| I-type (shift variation) | slli, srli, srai |
+| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu |
+
+\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks.
+
+## Caveats
+
+At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation:
+
+| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen |
+| --- | --- |
+| `RISCV_FORMAL_ILEN` | 32 |
+| `RISCV_FORMAL_XLEN` | 32 |
+| `RISCV_FORMAL_CSR_MISA` | undefined |
+| `RISCV_FORMAL_COMPRESSED` | undefined |
+| `RISCV_FORMAL_ALIGNED_MEM` | undefined |
+| `RISCV_FORMAL_ALTOPS` | defined |

insns/insn.py

@@ -0,0 +1,51 @@
+from nmigen import *
+
+class rvfi_insn(Elaboratable):
+    def __init__(self):
+        # Input ports
+        self.rvfi_valid = Signal(1)
+        self.rvfi_insn = Signal(32)
+        self.rvfi_pc_rdata = Signal(32)
+        self.rvfi_rs1_rdata = Signal(32)
+        self.rvfi_rs2_rdata = Signal(32)
+        self.rvfi_mem_rdata = Signal(32)
+
+        # Output ports
+        self.spec_valid = Signal(1)
+        self.spec_trap = Signal(1)
+        self.spec_rs1_addr = Signal(5)
+        self.spec_rs2_addr = Signal(5)
+        self.spec_rd_addr = Signal(5)
+        self.spec_rd_wdata = Signal(32)
+        self.spec_pc_wdata = Signal(32)
+        self.spec_mem_addr = Signal(32)
+        self.spec_mem_rmask = Signal(4)
+        self.spec_mem_wmask = Signal(4)
+        self.spec_mem_wdata = Signal(32)
+    def ports(self):
+        input_ports = [
+            self.rvfi_valid,
+            self.rvfi_insn,
+            self.rvfi_pc_rdata,
+            self.rvfi_rs1_rdata,
+            self.rvfi_rs2_rdata,
+            self.rvfi_mem_rdata
+        ]
+        output_ports = [
+            self.spec_valid,
+            self.spec_trap,
+            self.spec_rs1_addr,
+            self.spec_rs2_addr,
+            self.spec_rd_addr,
+            self.spec_rd_wdata,
+            self.spec_pc_wdata,
+            self.spec_mem_addr,
+            self.spec_mem_rmask,
+            self.spec_mem_wmask,
+            self.spec_mem_wdata
+        ]
+        return input_ports + output_ports
+    def elaborate(self, platform):
+        m = Module()
+
+        return m

insns/insn_I.py

@@ -0,0 +1,38 @@
+from insn import *
+
+class rvfi_insn_I(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_I, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rs1 = Signal(5)
+        self.insn_funct3 = Signal(3)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+        self.ialign16 = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_I, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_I, self).elaborate(platform)
+
+        # I-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
+        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+        m.d.comb += self.ialign16.eq(0)
+
+        # default assignments
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_I_shift.py

@@ -0,0 +1,38 @@
+from insn import *
+
+class rvfi_insn_I_shift(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_I_shift, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_funct6 = Signal(7)
+        self.insn_shamt = Signal(6)
+        self.insn_rs1 = Signal(5)
+        self.insn_funct3 = Signal(3)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_I_shift, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_I_shift, self).elaborate(platform)
+
+        # I-type instruction format (shift variation)
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32])
+        m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26])
+        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+
+        # default assignments
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_R.py

@@ -0,0 +1,37 @@
+from insn import *
+
+class rvfi_insn_R(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_R, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_funct7 = Signal(7)
+        self.insn_rs2 = Signal(5)
+        self.insn_rs1 = Signal(5)
+        self.insn_funct3 = Signal(3)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_R, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_R, self).elaborate(platform)
+
+        # R-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32])
+        m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
+        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+
+        # default assignments
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_S.py

@@ -0,0 +1,32 @@
+from insn import *
+class rvfi_insn_S(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_S, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rs2 = Signal(5)
+        self.insn_rs1 = Signal(5)
+        self.insn_funct3 = Signal(3)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_S, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_S, self).elaborate(platform)
+
+        # S-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
+        m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
+        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+
+        # default assignments
+        m.d.comb += self.spec_rd_addr.eq(0)
+        m.d.comb += self.spec_rd_wdata.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+
+        return m

insns/insn_SB.py

@@ -0,0 +1,38 @@
+from insn import *
+
+class rvfi_insn_SB(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_SB, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rs2 = Signal(5)
+        self.insn_rs1 = Signal(5)
+        self.insn_funct3 = Signal(3)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+        self.ialign16 = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_SB, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_SB, self).elaborate(platform)
+
+        # SB-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
+        m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
+        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
+        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+        m.d.comb += self.ialign16.eq(0)
+
+        # default assignments
+        m.d.comb += self.spec_rd_addr.eq(0)
+        m.d.comb += self.spec_rd_wdata.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_U.py

@@ -0,0 +1,33 @@
+from insn import *
+
+class rvfi_insn_U(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_U, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_U, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_U, self).elaborate(platform)
+
+        # U-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+
+        # Default assignments
+        m.d.comb += self.spec_rs1_addr.eq(0)
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_UJ.py

@@ -0,0 +1,34 @@
+from insn import *
+
+class rvfi_insn_UJ(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_UJ, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+        self.ialign16 = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_UJ, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_UJ, self).elaborate(platform)
+
+        # UJ-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+        m.d.comb += self.ialign16.eq(0)
+
+        # Default assignments
+        m.d.comb += self.spec_rs1_addr.eq(0)
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m

insns/insn_add.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_add(Elaboratable):
+class rvfi_insn_add(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_add, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_add, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_add, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # ADD instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_addi.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_addi(Elaboratable):
+class rvfi_insn_addi(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_addi, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_addi, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_addi, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # ADDI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata + self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_and.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_and(Elaboratable):
+class rvfi_insn_and(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_and, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_and, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_and, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # AND instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_andi.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_andi(Elaboratable):
+class rvfi_insn_andi(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_andi, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_andi, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_andi, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # ANDI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata & insn_imm)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata & self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_auipc.py

@@ -1,78 +1,17 @@
-from nmigen import *
+from insn_U import *
 
-class rvfi_insn_auipc(Elaboratable):
+class rvfi_insn_auipc(rvfi_insn_U):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_auipc, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_auipc, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_auipc, self).elaborate(platform)
-
-        # U-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # AUIPC instruction
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0010111))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111))
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
-        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + insn_imm, 0))
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs1_addr.eq(0)
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_beq.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_beq(Elaboratable):
+class rvfi_insn_beq(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_beq, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_beq, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_beq, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BEQ instruction
         cond = Signal(1)
         m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata)
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_bge.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_bge(Elaboratable):
+class rvfi_insn_bge(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_bge, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_bge, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_bge, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BGE instruction
         cond = Signal(1)
         m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata))
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b101) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_bgeu.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_bgeu(Elaboratable):
+class rvfi_insn_bgeu(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_bgeu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_bgeu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_bgeu, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BGEU instruction
         cond = Signal(1)
         m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata)
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_blt.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_blt(Elaboratable):
+class rvfi_insn_blt(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_blt, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_blt, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_blt, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BLT instruction
         cond = Signal(1)
         m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata))
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_bltu.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_bltu(Elaboratable):
+class rvfi_insn_bltu(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_bltu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_bltu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_bltu, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BLTU instruction
         cond = Signal(1)
         m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata)
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_bne.py

@@ -1,88 +1,22 @@
-from nmigen import *
+from insn_SB import *
 
-class rvfi_insn_bne(Elaboratable):
+class rvfi_insn_bne(rvfi_insn_SB):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_bne, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_bne, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_bne, self).elaborate(platform)
-
-        # SB-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # BNE instruction
         cond = Signal(1)
         m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata)
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4))
+        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b1100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_div.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_div(Elaboratable):
+class rvfi_insn_div(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_div, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_div, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_div, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # DIV instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_divu.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_divu(Elaboratable):
+class rvfi_insn_divu(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_divu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_divu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_divu, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # DIVU instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_jal.py

@@ -1,82 +1,20 @@
-from nmigen import *
+from insn_UJ import *
 
-class rvfi_insn_jal(Elaboratable):
+class rvfi_insn_jal(rvfi_insn_UJ):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_jal, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_jal, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_jal, self).elaborate(platform)
-
-        # UJ-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # JAL instruction
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq(self.rvfi_pc_rdata + insn_imm)
+        m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b1101111))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs1_addr.eq(0)
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_jalr.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_jalr(Elaboratable):
+class rvfi_insn_jalr(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_jalr, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_jalr, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_jalr, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
-        ialign16 = Signal(1)
-        m.d.comb += ialign16.eq(0)
 
         # JALR instruction
-        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        next_pc = Signal(32)
-        m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN))
+        m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100111))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
-        m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_lb.py

@@ -1,86 +1,25 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_lb(Elaboratable):
+class rvfi_insn_lb(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lb, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lb, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lb, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LB instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
         result = Signal(8)
         m.d.comb += result.eq(self.rvfi_mem_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b000) & (insn_opcode == 0b0000011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0000011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_lbu.py

@@ -1,86 +1,25 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_lbu(Elaboratable):
+class rvfi_insn_lbu(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lbu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lbu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lbu, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LBU instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
         result = Signal(8)
         m.d.comb += result.eq(self.rvfi_mem_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b100) & (insn_opcode == 0b0000011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_lh.py

@@ -1,86 +1,25 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_lh(Elaboratable):
+class rvfi_insn_lh(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lh, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lh, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lh, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LH instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
         result = Signal(16)
         m.d.comb += result.eq(self.rvfi_mem_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b001) & (insn_opcode == 0b0000011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_lhu.py

@@ -1,86 +1,25 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_lhu(Elaboratable):
+class rvfi_insn_lhu(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lhu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lhu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lhu, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LHU instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
         result = Signal(16)
         m.d.comb += result.eq(self.rvfi_mem_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b101) & (insn_opcode == 0b0000011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0000011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_lui.py

@@ -1,78 +1,17 @@
-from nmigen import *
+from insn_U import *
 
-class rvfi_insn_lui(Elaboratable):
+class rvfi_insn_lui(rvfi_insn_U):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lui, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lui, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lui, self).elaborate(platform)
-
-        # U-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LUI instruction
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0110111))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111))
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
-        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, insn_imm, 0))
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs1_addr.eq(0)
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_lw.py

@@ -1,86 +1,25 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_lw(Elaboratable):
+class rvfi_insn_lw(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_lw, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_lw, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_lw, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # LW instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
         result = Signal(32)
         m.d.comb += result.eq(self.rvfi_mem_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b010) & (insn_opcode == 0b0000011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
 
         return m

insns/insn_mul.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_mul(Elaboratable):
+class rvfi_insn_mul(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_mul, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_mul, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_mul, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # MUL instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_mulh.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_mulh(Elaboratable):
+class rvfi_insn_mulh(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_mulh, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_mulh, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_mulh, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # MULH instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_mulhsu.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_mulhsu(Elaboratable):
+class rvfi_insn_mulhsu(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_mulhsu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_mulhsu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_mulhsu, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # MULHSU instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0xea3969edecfbe137)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_mulhu.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_mulhu(Elaboratable):
+class rvfi_insn_mulhu(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_mulhu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_mulhu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_mulhu, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # MULHU instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_or.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_or(Elaboratable):
+class rvfi_insn_or(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_or, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_or, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_or, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # OR instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_ori.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_ori(Elaboratable):
+class rvfi_insn_ori(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_ori, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_ori, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_ori, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # ORI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata | insn_imm)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata | self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_rem.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_rem(Elaboratable):
+class rvfi_insn_rem(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_rem, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_rem, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_rem, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # REM instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_remu.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_remu(Elaboratable):
+class rvfi_insn_remu(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_remu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_remu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_remu, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # REMU instruction
-        altops_bitmask = Signal(64)
+        altops_bitmask = Signal(32)
         m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1)
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sb.py

@@ -1,84 +1,23 @@
-from nmigen import *
+from insn_S import *
 
-class rvfi_insn_sb(Elaboratable):
+class rvfi_insn_sb(rvfi_insn_S):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sb, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sb, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sb, self).elaborate(platform)
-
-        # S-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SB instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1)
         m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
 
         return m

insns/insn_sh.py

@@ -1,84 +1,23 @@
-from nmigen import *
+from insn_S import *
 
-class rvfi_insn_sh(Elaboratable):
+class rvfi_insn_sh(rvfi_insn_S):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sh, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sh, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sh, self).elaborate(platform)
-
-        # S-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SH instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b0100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1)
         m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
 
         return m

insns/insn_sll.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_sll(Elaboratable):
+class rvfi_insn_sll(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sll, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sll, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sll, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLL instruction
         shamt = Signal(6)
-        m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
+        m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5])
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_slli.py

@@ -1,86 +1,20 @@
-from nmigen import *
+from insn_I_shift import *
 
-class rvfi_insn_slli(Elaboratable):
+class rvfi_insn_slli(rvfi_insn_I_shift):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_slli, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_slli, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_slli, self).elaborate(platform)
-
-        # I-type instruction format (shift variation)
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct6 = Signal(7)
-        m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
-        insn_shamt = Signal(6)
-        m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLLI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata << insn_shamt)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5]))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_slt.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_slt(Elaboratable):
+class rvfi_insn_slt(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_slt, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_slt, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_slt, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLT instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_slti.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_slti(Elaboratable):
+class rvfi_insn_slti(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_slti, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_slti, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_slti, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLTI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(insn_imm))
+        m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm))
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sltiu.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_sltiu(Elaboratable):
+class rvfi_insn_sltiu(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sltiu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sltiu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sltiu, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLTIU instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata < insn_imm)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b011) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sltu.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_sltu(Elaboratable):
+class rvfi_insn_sltu(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sltu, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sltu, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sltu, self).elaborate(platform)
-
-        # R-type instruction format (shift variation)
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SLTU instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sra.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_sra(Elaboratable):
+class rvfi_insn_sra(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sra, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sra, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sra, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SRA instruction
         shamt = Signal(6)
-        m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
+        m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5])
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - shamt))) # https://stackoverflow.com/a/25207042
+        m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_srai.py

@@ -1,86 +1,20 @@
-from nmigen import *
+from insn_I_shift import *
 
-class rvfi_insn_srai(Elaboratable):
+class rvfi_insn_srai(rvfi_insn_I_shift):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_srai, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_srai, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_srai, self).elaborate(platform)
-
-        # I-type instruction format (shift variation)
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct6 = Signal(7)
-        m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
-        insn_shamt = Signal(6)
-        m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SRAI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq((self.rvfi_rs1_rdata >> insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - insn_shamt))) # https://stackoverflow.com/a/25207042
+        m.d.comb += result.eq((self.rvfi_rs1_rdata >> self.insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - self.insn_shamt))) # https://stackoverflow.com/a/25207042
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b010000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b010000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5]))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_srl.py

@@ -1,88 +1,23 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_srl(Elaboratable):
+class rvfi_insn_srl(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_srl, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_srl, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_srl, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SRL instruction
         shamt = Signal(6)
-        m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
+        m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5])
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_srli.py

@@ -1,86 +1,20 @@
-from nmigen import *
+from insn_I_shift import *
 
-class rvfi_insn_srli(Elaboratable):
+class rvfi_insn_srli(rvfi_insn_I_shift):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_srli, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_srli, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_srli, self).elaborate(platform)
-
-        # I-type instruction format (shift variation)
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct6 = Signal(7)
-        m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
-        insn_shamt = Signal(6)
-        m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SRLI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata >> insn_shamt)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata >> self.insn_shamt)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5]))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sub.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_sub(Elaboratable):
+class rvfi_insn_sub(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sub, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sub, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sub, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SUB instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_sw.py

@@ -1,84 +1,23 @@
-from nmigen import *
+from insn_S import *
 
-class rvfi_insn_sw(Elaboratable):
+class rvfi_insn_sw(rvfi_insn_S):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_sw, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_sw, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_sw, self).elaborate(platform)
-
-        # S-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # SW instruction
-        addr = Signal(self.RISCV_FORMAL_XLEN)
+        addr = Signal(32)
-        m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0100011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
         m.d.comb += self.spec_mem_addr.eq(addr)
         m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1)
         m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
-
-        # default assignments
-        m.d.comb += self.spec_rd_addr.eq(0)
-        m.d.comb += self.spec_rd_wdata.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
 
         return m

insns/insn_types.md

@@ -0,0 +1,11 @@
+# RV32IM Instruction Types
+
+| Instruction type | Instructions |
+| --- | --- |
+| U-type | lui, auipc |
+| UJ-type | jal |
+| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi |
+| SB-type | beq, bne, blt, bge, bltu, bgeu |
+| S-type | sb, sh, sw |
+| I-type (shift variation) | slli, srli, srai |
+| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu |

insns/insn_xor.py

@@ -1,86 +1,21 @@
-from nmigen import *
+from insn_R import *
 
-class rvfi_insn_xor(Elaboratable):
+class rvfi_insn_xor(rvfi_insn_R):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_xor, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_xor, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_xor, self).elaborate(platform)
-
-        # R-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_funct7 = Signal(7)
-        m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
-        insn_rs2 = Signal(5)
-        m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # XOR instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
         m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m

insns/insn_xori.py

@@ -1,84 +1,20 @@
-from nmigen import *
+from insn_I import *
 
-class rvfi_insn_xori(Elaboratable):
+class rvfi_insn_xori(rvfi_insn_I):
-    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+    def __init__(self):
-        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
+        super(rvfi_insn_xori, self).__init__()
-        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
-        self.rvfi_valid = Signal(1)
-        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
-        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_valid = Signal(1)
-        self.spec_trap = Signal(1)
-        self.spec_rs1_addr = Signal(5)
-        self.spec_rs2_addr = Signal(5)
-        self.spec_rd_addr = Signal(5)
-        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
-        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
-        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
     def ports(self):
-        input_ports = [
+        return super(rvfi_insn_xori, self).ports()
-            self.rvfi_valid,
-            self.rvfi_insn,
-            self.rvfi_pc_rdata,
-            self.rvfi_rs1_rdata,
-            self.rvfi_rs2_rdata,
-            self.rvfi_mem_rdata
-        ]
-        output_ports = [
-            self.spec_valid,
-            self.spec_trap,
-            self.spec_rs1_addr,
-            self.spec_rs2_addr,
-            self.spec_rd_addr,
-            self.spec_rd_wdata,
-            self.spec_pc_wdata,
-            self.spec_mem_addr,
-            self.spec_mem_rmask,
-            self.spec_mem_wmask,
-            self.spec_mem_wdata
-        ]
-        return input_ports + output_ports
     def elaborate(self, platform):
-        m = Module()
+        m = super(rvfi_insn_xori, self).elaborate(platform)
-
-        # I-type instruction format
-        insn_padding = Signal(self.RISCV_FORMAL_ILEN)
-        m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
-        insn_imm = Signal(self.RISCV_FORMAL_XLEN)
-        m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
-        insn_rs1 = Signal(5)
-        m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
-        insn_funct3 = Signal(3)
-        m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
-        insn_rd = Signal(5)
-        m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
-        insn_opcode = Signal(7)
-        m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
-
-        misa_ok = Signal(1)
-        m.d.comb += misa_ok.eq(1)
 
         # XORI instruction
-        result = Signal(self.RISCV_FORMAL_XLEN)
+        result = Signal(32)
-        m.d.comb += result.eq(self.rvfi_rs1_rdata ^ insn_imm)
+        m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.insn_imm)
-        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b0010011))
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0010011))
-        m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
-        m.d.comb += self.spec_rd_addr.eq(insn_rd)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
         m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
         m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
 
-        # default assignments
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_trap.eq(~misa_ok)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m