From c9c47ddc35dbeb183344dddebb3721a65a731ab2 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 12:06:51 +0800 Subject: [PATCH 01/84] Create general instruction class --- insns/insn_general.py | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 insns/insn_general.py diff --git a/insns/insn_general.py b/insns/insn_general.py new file mode 100644 index 0000000..41186ba --- /dev/null +++ b/insns/insn_general.py @@ -0,0 +1,50 @@ +from nmigen import * + +class rvfi_insn_generic(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + return input_ports + output_ports + def elaborate(self, platform): + m = Module() + + return m From 34c8b6cf3dfce631e2f002901364fe5ad6db0c59 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 12:45:32 +0800 Subject: [PATCH 02/84] Create U-type instruction format --- insns/insn_U_type.py | 33 +++++++++++++++++++++++++++++++++ insns/insn_general.py | 2 +- 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 insns/insn_U_type.py diff --git a/insns/insn_U_type.py b/insns/insn_U_type.py new file mode 100644 index 0000000..334d15c --- /dev/null +++ b/insns/insn_U_type.py @@ -0,0 +1,33 @@ +from insn_general import * + +class rvfi_insn_U_type(rvfi_insn_general): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + super(rvfi_insn_U_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_U_type, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_U_type, self).elaborate(platform) + + # U-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_general.py b/insns/insn_general.py index 41186ba..c649196 100644 --- a/insns/insn_general.py +++ b/insns/insn_general.py @@ -1,6 +1,6 @@ from nmigen import * -class rvfi_insn_generic(Elaboratable): +class rvfi_insn_general(Elaboratable): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN From 927c12e97cbb86d49b391594d8c0c606f53c981b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 12:55:57 +0800 Subject: [PATCH 03/84] Refactor LUI instruction --- insns/insn_lui.py | 77 +++++------------------------------------------ 1 file changed, 8 insertions(+), 69 deletions(-) diff --git a/insns/insn_lui.py b/insns/insn_lui.py index 870429e..36da7bc 100644 --- a/insns/insn_lui.py +++ b/insns/insn_lui.py @@ -1,78 +1,17 @@ -from nmigen import * +from insn_U_type import * -class rvfi_insn_lui(Elaboratable): +class rvfi_insn_lui(rvfi_insn_U_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lui, self).ports() def elaborate(self, platform): - m = Module() - - # U-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lui, self).elaborate(platform) # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, insn_imm, 0)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m From 3dc2a174fddcd333b735c18c42147922312217c0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:01:13 +0800 Subject: [PATCH 04/84] Refactor AUIPC instruction --- insns/insn_auipc.py | 79 ++++++--------------------------------------- 1 file changed, 9 insertions(+), 70 deletions(-) diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py index 02f0da5..905eab8 100644 --- a/insns/insn_auipc.py +++ b/insns/insn_auipc.py @@ -1,78 +1,17 @@ -from nmigen import * +from insn_U_type import * -class rvfi_insn_auipc(Elaboratable): +class rvfi_insn_auipc(rvfi_insn_U_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_auipc, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_auipc, self).ports() def elaborate(self, platform): - m = Module() + m = super(rvfi_insn_auipc, self).elaborate(platform) - # U-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + insn_imm, 0)) + # LUI instruction + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m From a84b6d50b8856d3898a79b43b3c3fe4ac4b2b9a0 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:15:17 +0800 Subject: [PATCH 05/84] Add UJ-type instruction format --- insns/insn_UJ_type.py | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 insns/insn_UJ_type.py diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py new file mode 100644 index 0000000..137d8be --- /dev/null +++ b/insns/insn_UJ_type.py @@ -0,0 +1,34 @@ +from insn_general import * + +class rvfi_insn_UJ_type(rvfi_insn_general): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + super(rvfi_insn_UJ_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_UJ_type, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_UJ_type, self).elaborate(platform) + + # UJ-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From 7846ba95ac6244690afbd49a5d090ffe149c2c87 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:34:52 +0800 Subject: [PATCH 06/84] Refactor JAL instruction --- insns/insn_jal.py | 80 ++++++----------------------------------------- 1 file changed, 9 insertions(+), 71 deletions(-) diff --git a/insns/insn_jal.py b/insns/insn_jal.py index 2670b76..1eaab3c 100644 --- a/insns/insn_jal.py +++ b/insns/insn_jal.py @@ -1,82 +1,20 @@ -from nmigen import * +from insn_UJ_type import * -class rvfi_insn_jal(Elaboratable): +class rvfi_insn_jal(rvfi_insn_UJ_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_jal, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_jal, self).ports() def elaborate(self, platform): - m = Module() - - # UJ-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_jal, self).elaborate(platform) # JAL instruction next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From e6c6f0462e72bbb34c0c055649cae87a5fb49d9c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:48:01 +0800 Subject: [PATCH 07/84] Add I-type instruction format --- insns/insn_I_type.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 insns/insn_I_type.py diff --git a/insns/insn_I_type.py b/insns/insn_I_type.py new file mode 100644 index 0000000..1ecf805 --- /dev/null +++ b/insns/insn_I_type.py @@ -0,0 +1,37 @@ +from insn_general import * + +class rvfi_insn_I_type(rvfi_insn_general): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + super(rvfi_insn_I_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_I_type, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I_type, self).elaborate(platform) + + # I-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From f4f5e94843844c32493fd240d3532363befa5503 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:56:30 +0800 Subject: [PATCH 08/84] Refactor JALR instruction --- insns/insn_jalr.py | 85 ++++++---------------------------------------- 1 file changed, 10 insertions(+), 75 deletions(-) diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py index 2529e8a..28ad496 100644 --- a/insns/insn_jalr.py +++ b/insns/insn_jalr.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_I_type import * -class rvfi_insn_jalr(Elaboratable): +class rvfi_insn_jalr(rvfi_insn_I_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_jalr, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_jalr, self).elaborate(platform) # JALR instruction next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 4a695c950d5f0d30f576ee8ef4b3cd9818088ac8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 14:03:59 +0800 Subject: [PATCH 09/84] Add SB-type instruction format --- insns/insn_SB_type.py | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/insn_SB_type.py diff --git a/insns/insn_SB_type.py b/insns/insn_SB_type.py new file mode 100644 index 0000000..d202fed --- /dev/null +++ b/insns/insn_SB_type.py @@ -0,0 +1,38 @@ +from insn_general import * + +class rvfi_insn_SB_type(rvfi_insn_general): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + super(rvfi_insn_SB_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_SB_type, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_SB_type, self).elaborate(platform) + + # SB-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From 3d1bb14baee8046db9bfefeadf33c273325c5c68 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 14:10:48 +0800 Subject: [PATCH 10/84] Refactor BEQ instruction --- insns/insn_beq.py | 86 ++++++----------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_beq.py b/insns/insn_beq.py index 063241c..6bb4708 100644 --- a/insns/insn_beq.py +++ b/insns/insn_beq.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_beq(Elaboratable): +class rvfi_insn_beq(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_beq, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_beq, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_beq, self).elaborate(platform) # BEQ instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 31f6847640c954ca21eb9104313476ccea8771b3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 14:14:24 +0800 Subject: [PATCH 11/84] Refactor BNE instruction --- insns/insn_bne.py | 86 ++++++----------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_bne.py b/insns/insn_bne.py index c6b0673..d4cb695 100644 --- a/insns/insn_bne.py +++ b/insns/insn_bne.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_bne(Elaboratable): +class rvfi_insn_bne(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_bne, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bne, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bne, self).elaborate(platform) # BNE instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 583d165ec1e5da9bd7a2fb5f2001905eba5f8738 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 15:42:10 +0800 Subject: [PATCH 12/84] Refactor BLT instruction --- insns/insn_blt.py | 86 ++++++----------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_blt.py b/insns/insn_blt.py index e5dda37..faf9db2 100644 --- a/insns/insn_blt.py +++ b/insns/insn_blt.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_blt(Elaboratable): +class rvfi_insn_blt(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_blt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_blt, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_blt, self).elaborate(platform) # BLT instruction cond = Signal(1) m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 847099e4def88a31cb41ac0babc27b636bdafebb Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 15:46:18 +0800 Subject: [PATCH 13/84] Refactor BGE instruction --- insns/insn_bge.py | 86 ++++++----------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_bge.py b/insns/insn_bge.py index 2f8ce08..f9f5a99 100644 --- a/insns/insn_bge.py +++ b/insns/insn_bge.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_bge(Elaboratable): +class rvfi_insn_bge(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_bge, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bge, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bge, self).elaborate(platform) # BGE instruction cond = Signal(1) m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b101) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 331cfda279e187dd95d99a1f9d3d057267a0ae58 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 15:49:56 +0800 Subject: [PATCH 14/84] Refactor BLTU instruction --- insns/insn_bltu.py | 86 ++++++---------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py index 5f44e4c..58d60d2 100644 --- a/insns/insn_bltu.py +++ b/insns/insn_bltu.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_bltu(Elaboratable): +class rvfi_insn_bltu(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_bltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bltu, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bltu, self).elaborate(platform) # BLTU instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From 9974db7e7b596f932d86667180b2d906aa03c242 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 15:53:39 +0800 Subject: [PATCH 15/84] Refactor BGEU instruction --- insns/insn_bgeu.py | 86 ++++++---------------------------------------- 1 file changed, 10 insertions(+), 76 deletions(-) diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py index 79472e2..a1aa664 100644 --- a/insns/insn_bgeu.py +++ b/insns/insn_bgeu.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB_type import * -class rvfi_insn_bgeu(Elaboratable): +class rvfi_insn_bgeu(rvfi_insn_SB_type): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + super(rvfi_insn_bgeu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bgeu, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bgeu, self).elaborate(platform) # BGEU instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m From e24ddd426978015a0140642564efd69d5836b564 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:07:47 +0800 Subject: [PATCH 16/84] Fix LUI instruction --- insns/insn_lui.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/insns/insn_lui.py b/insns/insn_lui.py index 36da7bc..73aa428 100644 --- a/insns/insn_lui.py +++ b/insns/insn_lui.py @@ -14,4 +14,13 @@ class rvfi_insn_lui(rvfi_insn_U_type): m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + # default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From 4d62caadc7a6ab736e1f1c65f8abbff0feab8233 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:08:24 +0800 Subject: [PATCH 17/84] Fix U-type instruction format --- insns/insn_U_type.py | 9 --------- 1 file changed, 9 deletions(-) diff --git a/insns/insn_U_type.py b/insns/insn_U_type.py index 334d15c..adc1257 100644 --- a/insns/insn_U_type.py +++ b/insns/insn_U_type.py @@ -21,13 +21,4 @@ class rvfi_insn_U_type(rvfi_insn_general): m.d.comb += self.misa_ok.eq(1) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m From 6cff1038bed55e6f250f0fef07c28039f0d78e7b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:12:10 +0800 Subject: [PATCH 18/84] Fix AUIPC instruction --- insns/insn_auipc.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py index 905eab8..425a7db 100644 --- a/insns/insn_auipc.py +++ b/insns/insn_auipc.py @@ -8,10 +8,19 @@ class rvfi_insn_auipc(rvfi_insn_U_type): def elaborate(self, platform): m = super(rvfi_insn_auipc, self).elaborate(platform) - # LUI instruction + # AUIPC instruction m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + # default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From b583ab728fbe71296f14a0850d24b8dcc169aa79 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:16:06 +0800 Subject: [PATCH 19/84] Fix JAL instruction --- insns/insn_UJ_type.py | 8 -------- insns/insn_jal.py | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py index 137d8be..b5a6ade 100644 --- a/insns/insn_UJ_type.py +++ b/insns/insn_UJ_type.py @@ -23,12 +23,4 @@ class rvfi_insn_UJ_type(rvfi_insn_general): m.d.comb += self.misa_ok.eq(1) m.d.comb += self.ialign16.eq(0) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py index 1eaab3c..baf1c35 100644 --- a/insns/insn_jal.py +++ b/insns/insn_jal.py @@ -17,4 +17,12 @@ class rvfi_insn_jal(rvfi_insn_UJ_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From 9ddc5563f75b2e5208a76839aaae4de90d0babb7 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:19:01 +0800 Subject: [PATCH 20/84] Fix JALR instruction --- insns/insn_I_type.py | 7 ------- insns/insn_jalr.py | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/insns/insn_I_type.py b/insns/insn_I_type.py index 1ecf805..51a71d4 100644 --- a/insns/insn_I_type.py +++ b/insns/insn_I_type.py @@ -27,11 +27,4 @@ class rvfi_insn_I_type(rvfi_insn_general): m.d.comb += self.misa_ok.eq(1) m.d.comb += self.ialign16.eq(0) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py index 28ad496..e4f3540 100644 --- a/insns/insn_jalr.py +++ b/insns/insn_jalr.py @@ -18,4 +18,11 @@ class rvfi_insn_jalr(rvfi_insn_I_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From 4146a2ed207057ad42a9095c01f1fb9850200039 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:24:04 +0800 Subject: [PATCH 21/84] Fix BEQ instruction --- insns/insn_SB_type.py | 8 -------- insns/insn_beq.py | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/insns/insn_SB_type.py b/insns/insn_SB_type.py index d202fed..e92ef6a 100644 --- a/insns/insn_SB_type.py +++ b/insns/insn_SB_type.py @@ -27,12 +27,4 @@ class rvfi_insn_SB_type(rvfi_insn_general): m.d.comb += self.misa_ok.eq(1) m.d.comb += self.ialign16.eq(0) - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py index 6bb4708..48aa0c6 100644 --- a/insns/insn_beq.py +++ b/insns/insn_beq.py @@ -18,5 +18,13 @@ class rvfi_insn_beq(rvfi_insn_SB_type): m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) return m From 65e4b68517793d7a985a94b40aa50bc71c12fddd Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:26:29 +0800 Subject: [PATCH 22/84] Fix BNE instruction --- insns/insn_bne.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/insns/insn_bne.py b/insns/insn_bne.py index d4cb695..cb7551b 100644 --- a/insns/insn_bne.py +++ b/insns/insn_bne.py @@ -19,4 +19,12 @@ class rvfi_insn_bne(rvfi_insn_SB_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From d0de67d09cf1c10f783cda2173f8dba46f4d8c26 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:28:52 +0800 Subject: [PATCH 23/84] Fix BLT instruction --- insns/insn_blt.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/insns/insn_blt.py b/insns/insn_blt.py index faf9db2..35d8121 100644 --- a/insns/insn_blt.py +++ b/insns/insn_blt.py @@ -19,4 +19,12 @@ class rvfi_insn_blt(rvfi_insn_SB_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From b8e8d10648274eb01ef9c84ace5dbe7c1fed3720 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:31:23 +0800 Subject: [PATCH 24/84] Fix BGE instruction --- insns/insn_bge.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/insns/insn_bge.py b/insns/insn_bge.py index f9f5a99..62bee30 100644 --- a/insns/insn_bge.py +++ b/insns/insn_bge.py @@ -19,4 +19,12 @@ class rvfi_insn_bge(rvfi_insn_SB_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From 83e7ab1f057c5c3cb9832ae13ba8ddc565ee3cad Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 16:33:49 +0800 Subject: [PATCH 25/84] Fix BLTU instruction --- insns/insn_bltu.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py index 58d60d2..36b6652 100644 --- a/insns/insn_bltu.py +++ b/insns/insn_bltu.py @@ -19,4 +19,12 @@ class rvfi_insn_bltu(rvfi_insn_SB_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From e3273c7e5129669075e78a18916834a16cec88fe Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 17:37:13 +0800 Subject: [PATCH 26/84] Fix BGEU instruction --- insns/insn_bgeu.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py index a1aa664..64b95e7 100644 --- a/insns/insn_bgeu.py +++ b/insns/insn_bgeu.py @@ -19,4 +19,12 @@ class rvfi_insn_bgeu(rvfi_insn_SB_type): m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + return m From aa9967e83d329945e35b546251277fdd9fb9904b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 11:17:58 +0800 Subject: [PATCH 27/84] Start over in insns/ --- insns/insn_I_type.py | 30 --------------- insns/insn_SB_type.py | 30 --------------- insns/insn_UJ_type.py | 26 ------------- insns/insn_U_type.py | 24 ------------ insns/insn_add.py | 86 ------------------------------------------ insns/insn_addi.py | 84 ----------------------------------------- insns/insn_and.py | 86 ------------------------------------------ insns/insn_andi.py | 84 ----------------------------------------- insns/insn_auipc.py | 26 ------------- insns/insn_beq.py | 30 --------------- insns/insn_bge.py | 30 --------------- insns/insn_bgeu.py | 30 --------------- insns/insn_blt.py | 30 --------------- insns/insn_bltu.py | 30 --------------- insns/insn_bne.py | 30 --------------- insns/insn_div.py | 88 ------------------------------------------- insns/insn_divu.py | 88 ------------------------------------------- insns/insn_general.py | 50 ------------------------ insns/insn_jal.py | 28 -------------- insns/insn_jalr.py | 28 -------------- insns/insn_lb.py | 86 ------------------------------------------ insns/insn_lbu.py | 86 ------------------------------------------ insns/insn_lh.py | 86 ------------------------------------------ insns/insn_lhu.py | 86 ------------------------------------------ insns/insn_lui.py | 26 ------------- insns/insn_lw.py | 86 ------------------------------------------ insns/insn_mul.py | 88 ------------------------------------------- insns/insn_mulh.py | 88 ------------------------------------------- insns/insn_mulhsu.py | 88 ------------------------------------------- insns/insn_mulhu.py | 88 ------------------------------------------- insns/insn_or.py | 86 ------------------------------------------ insns/insn_ori.py | 84 ----------------------------------------- insns/insn_rem.py | 88 ------------------------------------------- insns/insn_remu.py | 88 ------------------------------------------- insns/insn_sb.py | 84 ----------------------------------------- insns/insn_sh.py | 84 ----------------------------------------- insns/insn_sll.py | 88 ------------------------------------------- insns/insn_slli.py | 86 ------------------------------------------ insns/insn_slt.py | 86 ------------------------------------------ insns/insn_slti.py | 84 ----------------------------------------- insns/insn_sltiu.py | 84 ----------------------------------------- insns/insn_sltu.py | 86 ------------------------------------------ insns/insn_sra.py | 88 ------------------------------------------- insns/insn_srai.py | 86 ------------------------------------------ insns/insn_srl.py | 88 ------------------------------------------- insns/insn_srli.py | 86 ------------------------------------------ insns/insn_sub.py | 86 ------------------------------------------ insns/insn_sw.py | 84 ----------------------------------------- insns/insn_xor.py | 86 ------------------------------------------ insns/insn_xori.py | 84 ----------------------------------------- 50 files changed, 3462 deletions(-) delete mode 100644 insns/insn_I_type.py delete mode 100644 insns/insn_SB_type.py delete mode 100644 insns/insn_UJ_type.py delete mode 100644 insns/insn_U_type.py delete mode 100644 insns/insn_add.py delete mode 100644 insns/insn_addi.py delete mode 100644 insns/insn_and.py delete mode 100644 insns/insn_andi.py delete mode 100644 insns/insn_auipc.py delete mode 100644 insns/insn_beq.py delete mode 100644 insns/insn_bge.py delete mode 100644 insns/insn_bgeu.py delete mode 100644 insns/insn_blt.py delete mode 100644 insns/insn_bltu.py delete mode 100644 insns/insn_bne.py delete mode 100644 insns/insn_div.py delete mode 100644 insns/insn_divu.py delete mode 100644 insns/insn_general.py delete mode 100644 insns/insn_jal.py delete mode 100644 insns/insn_jalr.py delete mode 100644 insns/insn_lb.py delete mode 100644 insns/insn_lbu.py delete mode 100644 insns/insn_lh.py delete mode 100644 insns/insn_lhu.py delete mode 100644 insns/insn_lui.py delete mode 100644 insns/insn_lw.py delete mode 100644 insns/insn_mul.py delete mode 100644 insns/insn_mulh.py delete mode 100644 insns/insn_mulhsu.py delete mode 100644 insns/insn_mulhu.py delete mode 100644 insns/insn_or.py delete mode 100644 insns/insn_ori.py delete mode 100644 insns/insn_rem.py delete mode 100644 insns/insn_remu.py delete mode 100644 insns/insn_sb.py delete mode 100644 insns/insn_sh.py delete mode 100644 insns/insn_sll.py delete mode 100644 insns/insn_slli.py delete mode 100644 insns/insn_slt.py delete mode 100644 insns/insn_slti.py delete mode 100644 insns/insn_sltiu.py delete mode 100644 insns/insn_sltu.py delete mode 100644 insns/insn_sra.py delete mode 100644 insns/insn_srai.py delete mode 100644 insns/insn_srl.py delete mode 100644 insns/insn_srli.py delete mode 100644 insns/insn_sub.py delete mode 100644 insns/insn_sw.py delete mode 100644 insns/insn_xor.py delete mode 100644 insns/insn_xori.py diff --git a/insns/insn_I_type.py b/insns/insn_I_type.py deleted file mode 100644 index 51a71d4..0000000 --- a/insns/insn_I_type.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_general import * - -class rvfi_insn_I_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_I_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_I_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I_type, self).elaborate(platform) - - # I-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_SB_type.py b/insns/insn_SB_type.py deleted file mode 100644 index e92ef6a..0000000 --- a/insns/insn_SB_type.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_general import * - -class rvfi_insn_SB_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_SB_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_SB_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_SB_type, self).elaborate(platform) - - # SB-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py deleted file mode 100644 index b5a6ade..0000000 --- a/insns/insn_UJ_type.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_general import * - -class rvfi_insn_UJ_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_UJ_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_UJ_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_UJ_type, self).elaborate(platform) - - # UJ-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_U_type.py b/insns/insn_U_type.py deleted file mode 100644 index adc1257..0000000 --- a/insns/insn_U_type.py +++ /dev/null @@ -1,24 +0,0 @@ -from insn_general import * - -class rvfi_insn_U_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_U_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_U_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_U_type, self).elaborate(platform) - - # U-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - return m diff --git a/insns/insn_add.py b/insns/insn_add.py deleted file mode 100644 index d995dff..0000000 --- a/insns/insn_add.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_add(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ADD instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_addi.py b/insns/insn_addi.py deleted file mode 100644 index 634279d..0000000 --- a/insns/insn_addi.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_addi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ADDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_and.py b/insns/insn_and.py deleted file mode 100644 index e27275b..0000000 --- a/insns/insn_and.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_and(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # AND instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_andi.py b/insns/insn_andi.py deleted file mode 100644 index 5f3a91d..0000000 --- a/insns/insn_andi.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_andi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ANDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata & insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py deleted file mode 100644 index 425a7db..0000000 --- a/insns/insn_auipc.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_U_type import * - -class rvfi_insn_auipc(rvfi_insn_U_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_auipc, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_auipc, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_auipc, self).elaborate(platform) - - # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py deleted file mode 100644 index 48aa0c6..0000000 --- a/insns/insn_beq.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_beq(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_beq, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_beq, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_beq, self).elaborate(platform) - - # BEQ instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bge.py b/insns/insn_bge.py deleted file mode 100644 index 62bee30..0000000 --- a/insns/insn_bge.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bge(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bge, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bge, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bge, self).elaborate(platform) - - # BGE instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py deleted file mode 100644 index 64b95e7..0000000 --- a/insns/insn_bgeu.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bgeu(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bgeu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bgeu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bgeu, self).elaborate(platform) - - # BGEU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_blt.py b/insns/insn_blt.py deleted file mode 100644 index 35d8121..0000000 --- a/insns/insn_blt.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_blt(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_blt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_blt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_blt, self).elaborate(platform) - - # BLT instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py deleted file mode 100644 index 36b6652..0000000 --- a/insns/insn_bltu.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bltu(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bltu, self).elaborate(platform) - - # BLTU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bne.py b/insns/insn_bne.py deleted file mode 100644 index cb7551b..0000000 --- a/insns/insn_bne.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bne(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bne, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bne, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bne, self).elaborate(platform) - - # BNE instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_div.py b/insns/insn_div.py deleted file mode 100644 index 5d71a32..0000000 --- a/insns/insn_div.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_div(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # DIV instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_divu.py b/insns/insn_divu.py deleted file mode 100644 index c5677f6..0000000 --- a/insns/insn_divu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_divu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # DIVU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_general.py b/insns/insn_general.py deleted file mode 100644 index c649196..0000000 --- a/insns/insn_general.py +++ /dev/null @@ -1,50 +0,0 @@ -from nmigen import * - -class rvfi_insn_general(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py deleted file mode 100644 index baf1c35..0000000 --- a/insns/insn_jal.py +++ /dev/null @@ -1,28 +0,0 @@ -from insn_UJ_type import * - -class rvfi_insn_jal(rvfi_insn_UJ_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_jal, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_jal, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jal, self).elaborate(platform) - - # JAL instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py deleted file mode 100644 index e4f3540..0000000 --- a/insns/insn_jalr.py +++ /dev/null @@ -1,28 +0,0 @@ -from insn_I_type import * - -class rvfi_insn_jalr(rvfi_insn_I_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_jalr, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jalr, self).elaborate(platform) - - # JALR instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lb.py b/insns/insn_lb.py deleted file mode 100644 index 10d2561..0000000 --- a/insns/insn_lb.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b000) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py deleted file mode 100644 index db836ad..0000000 --- a/insns/insn_lbu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lbu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LBU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b100) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lh.py b/insns/insn_lh.py deleted file mode 100644 index c6a00fc..0000000 --- a/insns/insn_lh.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b001) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py deleted file mode 100644 index 0f1c722..0000000 --- a/insns/insn_lhu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LHU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b101) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lui.py b/insns/insn_lui.py deleted file mode 100644 index 73aa428..0000000 --- a/insns/insn_lui.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_U_type import * - -class rvfi_insn_lui(rvfi_insn_U_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_lui, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lui, self).elaborate(platform) - - # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lw.py b/insns/insn_lw.py deleted file mode 100644 index 4507283..0000000 --- a/insns/insn_lw.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b010) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mul.py b/insns/insn_mul.py deleted file mode 100644 index 2e45dfd..0000000 --- a/insns/insn_mul.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mul(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MUL instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py deleted file mode 100644 index 05c93b6..0000000 --- a/insns/insn_mulh.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULH instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py deleted file mode 100644 index f8e957c..0000000 --- a/insns/insn_mulhsu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulhsu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULHSU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py deleted file mode 100644 index 685a6c3..0000000 --- a/insns/insn_mulhu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULHU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_or.py b/insns/insn_or.py deleted file mode 100644 index 85ca004..0000000 --- a/insns/insn_or.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_or(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # OR instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_ori.py b/insns/insn_ori.py deleted file mode 100644 index e4f8683..0000000 --- a/insns/insn_ori.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_ori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata | insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_rem.py b/insns/insn_rem.py deleted file mode 100644 index 3feba03..0000000 --- a/insns/insn_rem.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_rem(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # REM instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_remu.py b/insns/insn_remu.py deleted file mode 100644 index 068ac62..0000000 --- a/insns/insn_remu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_remu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # REMU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sb.py b/insns/insn_sb.py deleted file mode 100644 index e7a25b6..0000000 --- a/insns/insn_sb.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_sh.py b/insns/insn_sh.py deleted file mode 100644 index f85446b..0000000 --- a/insns/insn_sh.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_sll.py b/insns/insn_sll.py deleted file mode 100644 index 08377af..0000000 --- a/insns/insn_sll.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_sll(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slli.py b/insns/insn_slli.py deleted file mode 100644 index 5c6cf43..0000000 --- a/insns/insn_slli.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_slli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata << insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slt.py b/insns/insn_slt.py deleted file mode 100644 index e3ec0e2..0000000 --- a/insns/insn_slt.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_slt(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLT instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slti.py b/insns/insn_slti.py deleted file mode 100644 index 01e2863..0000000 --- a/insns/insn_slti.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_slti(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(insn_imm)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py deleted file mode 100644 index 2f1a005..0000000 --- a/insns/insn_sltiu.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sltiu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTIU instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata < insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b011) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py deleted file mode 100644 index 810f4e7..0000000 --- a/insns/insn_sltu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_sltu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTU instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sra.py b/insns/insn_sra.py deleted file mode 100644 index a3c3d04..0000000 --- a/insns/insn_sra.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_sra(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRA instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srai.py b/insns/insn_srai.py deleted file mode 100644 index a9c4efb..0000000 --- a/insns/insn_srai.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_srai(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRAI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - insn_shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b010000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srl.py b/insns/insn_srl.py deleted file mode 100644 index e72766a..0000000 --- a/insns/insn_srl.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_srl(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srli.py b/insns/insn_srli.py deleted file mode 100644 index d8fdc27..0000000 --- a/insns/insn_srli.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_srli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sub.py b/insns/insn_sub.py deleted file mode 100644 index a1dc233..0000000 --- a/insns/insn_sub.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_sub(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SUB instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sw.py b/insns/insn_sw.py deleted file mode 100644 index e96ec3f..0000000 --- a/insns/insn_sw.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_xor.py b/insns/insn_xor.py deleted file mode 100644 index a713d20..0000000 --- a/insns/insn_xor.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_xor(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # XOR instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_xori.py b/insns/insn_xori.py deleted file mode 100644 index 19c69e0..0000000 --- a/insns/insn_xori.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_xori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # XORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m From 29c5e52574e3461249df2da305eed4bca82fd993 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 11:56:22 +0800 Subject: [PATCH 28/84] Categorize RV32IM instructions by type --- insns/insn_types.md | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/insn_types.md diff --git a/insns/insn_types.md b/insns/insn_types.md new file mode 100644 index 0000000..5228a1f --- /dev/null +++ b/insns/insn_types.md @@ -0,0 +1,11 @@ +# RV32IM Instruction Types + +| Instruction type | Instructions | +| --- | --- | +| U-type | lui, auipc | +| UJ-type | jal | +| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | +| SB-type | beq, bne, blt, bge, bltu, bgeu | +| S-type | sb, sh, sw | +| I-type (shift variation) | slli, srli, srai | +| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | From 5274e5b1f1b46aedadb69f37aa3984c71d4ff55e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 13:06:03 +0800 Subject: [PATCH 29/84] Add generic instruction class --- insns/insn.py | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 insns/insn.py diff --git a/insns/insn.py b/insns/insn.py new file mode 100644 index 0000000..4588ff3 --- /dev/null +++ b/insns/insn.py @@ -0,0 +1,51 @@ +from nmigen import * + +class rvfi_insn(Elaboratable): + def __init__(self): + # Input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(32) + self.rvfi_pc_rdata = Signal(32) + self.rvfi_rs1_rdata = Signal(32) + self.rvfi_rs2_rdata = Signal(32) + self.rvfi_mem_rdata = Signal(32) + + # Output ports + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(32) + self.spec_pc_wdata = Signal(32) + self.spec_mem_addr = Signal(32) + self.spec_mem_rmask = Signal(4) + self.spec_mem_wmask = Signal(4) + self.spec_mem_wdata = Signal(32) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + return input_ports + output_ports + def elaborate(self, platform): + m = Module() + + return m From 9cbed8f1473f576c78ec95cdbc04e29d7e6d05d2 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 13:29:48 +0800 Subject: [PATCH 30/84] Add U-type instruction class --- insns/insn_U.py | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 insns/insn_U.py diff --git a/insns/insn_U.py b/insns/insn_U.py new file mode 100644 index 0000000..aec6828 --- /dev/null +++ b/insns/insn_U.py @@ -0,0 +1,33 @@ +from insn import * + +class rvfi_insn_U(rvfi_insn): + def __init__(self): + super(rvfi_insn_U, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_U, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_U, self).elaborate(platform) + + # U-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # Default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From 05266b847458dc66e92291b7fa9cf42b80c4148c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 13:40:40 +0800 Subject: [PATCH 31/84] Add LUI instruction --- insns/insn_lui.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 insns/insn_lui.py diff --git a/insns/insn_lui.py b/insns/insn_lui.py new file mode 100644 index 0000000..42aa764 --- /dev/null +++ b/insns/insn_lui.py @@ -0,0 +1,17 @@ +from insn_U import * + +class rvfi_insn_lui(rvfi_insn_U): + def __init__(self): + super(rvfi_insn_lui, self).__init__() + def ports(self): + return super(rvfi_insn_lui, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lui, self).elaborate(platform) + + # LUI instruction + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 7ddfa890dc80d8e911188f9311de28dd8f77c5c3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 13:44:22 +0800 Subject: [PATCH 32/84] Add AUIPC instruction --- insns/insn_auipc.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 insns/insn_auipc.py diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py new file mode 100644 index 0000000..07a9f63 --- /dev/null +++ b/insns/insn_auipc.py @@ -0,0 +1,17 @@ +from insn_U import * + +class rvfi_insn_auipc(rvfi_insn_U): + def __init__(self): + super(rvfi_insn_auipc, self).__init__() + def ports(self): + return super(rvfi_insn_auipc, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_auipc, self).elaborate(platform) + + # AUIPC instruction + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From b6a68b5b15f1a3a052994964ce94b569e6f74a7f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 13:57:52 +0800 Subject: [PATCH 33/84] Add UJ-type instruction class --- insns/insn_UJ.py | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 insns/insn_UJ.py diff --git a/insns/insn_UJ.py b/insns/insn_UJ.py new file mode 100644 index 0000000..d5d2b8f --- /dev/null +++ b/insns/insn_UJ.py @@ -0,0 +1,34 @@ +from insn import * + +class rvfi_insn_UJ(rvfi_insn): + def __init__(self): + super(rvfi_insn_UJ, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_UJ, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_UJ, self).elaborate(platform) + + # UJ-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # Default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From 67cba5bf12d5e1be47e371f10cf0267a58cebb87 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 14:06:55 +0800 Subject: [PATCH 34/84] Add JAL instruction --- insns/insn_jal.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_jal.py diff --git a/insns/insn_jal.py b/insns/insn_jal.py new file mode 100644 index 0000000..c95cb14 --- /dev/null +++ b/insns/insn_jal.py @@ -0,0 +1,20 @@ +from insn_UJ import * + +class rvfi_insn_jal(rvfi_insn_UJ): + def __init__(self): + super(rvfi_insn_jal, self).__init__() + def ports(self): + return super(rvfi_insn_jal, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_jal, self).elaborate(platform) + + # JAL instruction + next_pc = Signal(32) + m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From 08150e1ecdfeb67d8bcf0e121c5f2b8937473612 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 14:26:27 +0800 Subject: [PATCH 35/84] Add I-type instruction class --- insns/insn_I.py | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/insn_I.py diff --git a/insns/insn_I.py b/insns/insn_I.py new file mode 100644 index 0000000..3d0c7e3 --- /dev/null +++ b/insns/insn_I.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_I(rvfi_insn): + def __init__(self): + super(rvfi_insn_I, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_I, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I, self).elaborate(platform) + + # I-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From ecba1dc3e7e9eef703c61ace9b7eb25a59bd5e1f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:07:15 +0800 Subject: [PATCH 36/84] Add JALR instruction --- insns/insn_jalr.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_jalr.py diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py new file mode 100644 index 0000000..9ea4736 --- /dev/null +++ b/insns/insn_jalr.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_jalr(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_jalr, self).__init__() + def ports(self): + return super(rvfi_insn_jalr, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_jalr, self).elaborate(platform) + + next_pc = Signal(32) + m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From d525a89ccb2d0c4d32ee2b1ce5b3567711cb83ff Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:14:48 +0800 Subject: [PATCH 37/84] Add LB instruction --- insns/insn_lb.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/insn_lb.py diff --git a/insns/insn_lb.py b/insns/insn_lb.py new file mode 100644 index 0000000..4c3fba6 --- /dev/null +++ b/insns/insn_lb.py @@ -0,0 +1,25 @@ +from insn_I import * + +class rvfi_insn_lb(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lb, self).__init__() + def ports(self): + return super(rvfi_insn_lb, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lb, self).elaborate(platform) + + # LB instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + result = Signal(8) + m.d.comb += result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From ecfe8b11c4965e959c93d2be26bbddd361f69f42 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:15:17 +0800 Subject: [PATCH 38/84] Fix JALR instruction --- insns/insn_jalr.py | 1 + 1 file changed, 1 insertion(+) diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py index 9ea4736..56dddd0 100644 --- a/insns/insn_jalr.py +++ b/insns/insn_jalr.py @@ -8,6 +8,7 @@ class rvfi_insn_jalr(rvfi_insn_I): def elaborate(self, platform): m = super(rvfi_insn_jalr, self).elaborate(platform) + # JALR instruction next_pc = Signal(32) m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) From 96015ee5d9b66e0f657916395272c6dfdb566c81 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:19:04 +0800 Subject: [PATCH 39/84] Add LH instruction --- insns/insn_lh.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/insn_lh.py diff --git a/insns/insn_lh.py b/insns/insn_lh.py new file mode 100644 index 0000000..34c7f93 --- /dev/null +++ b/insns/insn_lh.py @@ -0,0 +1,25 @@ +from insn_I import * + +class rvfi_insn_lh(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lh, self).__init__() + def ports(self): + return super(rvfi_insn_lh, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lh, self).elaborate(platform) + + # LH instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + result = Signal(16) + m.d.comb += result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From dc31087f7349e7ea896b4266565e827ce6d06e47 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:27:36 +0800 Subject: [PATCH 40/84] Add LW instruction --- insns/insn_lw.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/insn_lw.py diff --git a/insns/insn_lw.py b/insns/insn_lw.py new file mode 100644 index 0000000..5e956e9 --- /dev/null +++ b/insns/insn_lw.py @@ -0,0 +1,25 @@ +from insn_I import * + +class rvfi_insn_lw(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lw, self).__init__() + def ports(self): + return super(rvfi_insn_lw, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lw, self).elaborate(platform) + + # LW instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From e3f0727e9c5284018f9152cf3846934a6ed25999 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:31:25 +0800 Subject: [PATCH 41/84] Add LBU instruction --- insns/insn_lbu.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/insn_lbu.py diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py new file mode 100644 index 0000000..3961c99 --- /dev/null +++ b/insns/insn_lbu.py @@ -0,0 +1,25 @@ +from insn_I import * + +class rvfi_insn_lbu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lbu, self).__init__() + def ports(self): + return super(rvfi_insn_lbu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lbu, self).elaborate(platform) + + # LBU instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + result = Signal(8) + m.d.comb += result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From cf8033a8bb4e3b63923b726cb47bd54515b09d1c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:35:06 +0800 Subject: [PATCH 42/84] Add LHU instruction --- insns/insn_lhu.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 insns/insn_lhu.py diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py new file mode 100644 index 0000000..b050668 --- /dev/null +++ b/insns/insn_lhu.py @@ -0,0 +1,25 @@ +from insn_I import * + +class rvfi_insn_lhu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lhu, self).__init__() + def ports(self): + return super(rvfi_insn_lhu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_lhu, self).elaborate(platform) + + # LHU instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + result = Signal(16) + m.d.comb += result.eq(self.rvfi_mem_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From a9bc0629bdbc985661600d263f5caefae28c7f08 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:39:32 +0800 Subject: [PATCH 43/84] Add ADDI instruction --- insns/insn_addi.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_addi.py diff --git a/insns/insn_addi.py b/insns/insn_addi.py new file mode 100644 index 0000000..70c7537 --- /dev/null +++ b/insns/insn_addi.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_addi(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_addi, self).__init__() + def ports(self): + return super(rvfi_insn_addi, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_addi, self).elaborate(platform) + + # ADDI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 305d2195be701092c3a9dda2ef003c4939d773da Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:42:29 +0800 Subject: [PATCH 44/84] Add SLTI instruction --- insns/insn_slti.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_slti.py diff --git a/insns/insn_slti.py b/insns/insn_slti.py new file mode 100644 index 0000000..a84f502 --- /dev/null +++ b/insns/insn_slti.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_slti(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_slti, self).__init__() + def ports(self): + return super(rvfi_insn_slti, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_slti, self).elaborate(platform) + + # SLTI instruction + result = Signal(32) + m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From e49476746edd9aee890906bc108c27bc5f809506 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:45:15 +0800 Subject: [PATCH 45/84] Add SLTIU instruction --- insns/insn_sltiu.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_sltiu.py diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py new file mode 100644 index 0000000..717dfef --- /dev/null +++ b/insns/insn_sltiu.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_sltiu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_sltiu, self).__init__() + def ports(self): + return super(rvfi_insn_sltiu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sltiu, self).elaborate(platform) + + # SLTIU instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From bf80a13d55c1d29759ab2b478af2fee575068992 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:48:00 +0800 Subject: [PATCH 46/84] Add XORI instruction --- insns/insn_xori.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_xori.py diff --git a/insns/insn_xori.py b/insns/insn_xori.py new file mode 100644 index 0000000..647067d --- /dev/null +++ b/insns/insn_xori.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_xori(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_xori, self).__init__() + def ports(self): + return super(rvfi_insn_xori, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_xori, self).elaborate(platform) + + # XORI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 912580dda814a8387e9fe6e13e86829324629a3e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:49:59 +0800 Subject: [PATCH 47/84] Add ORI instruction --- insns/insn_ori.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_ori.py diff --git a/insns/insn_ori.py b/insns/insn_ori.py new file mode 100644 index 0000000..3d4bb82 --- /dev/null +++ b/insns/insn_ori.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_ori(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_ori, self).__init__() + def ports(self): + return super(rvfi_insn_ori, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_ori, self).elaborate(platform) + + # ORI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata | self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 663b0b3b4841fdc578d47f4cb5dda644b975ee0f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:51:59 +0800 Subject: [PATCH 48/84] Add ANDI instruction --- insns/insn_andi.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_andi.py diff --git a/insns/insn_andi.py b/insns/insn_andi.py new file mode 100644 index 0000000..6d4c0fa --- /dev/null +++ b/insns/insn_andi.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_andi(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_andi, self).__init__() + def ports(self): + return super(rvfi_insn_andi, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_andi, self).elaborate(platform) + + # ANDI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata & self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 33ecb317b2b91c1d1c1825c95d530252605c153c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:19:01 +0800 Subject: [PATCH 49/84] Add SB-type instruction --- insns/insn_SB.py | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/insn_SB.py diff --git a/insns/insn_SB.py b/insns/insn_SB.py new file mode 100644 index 0000000..352f0c6 --- /dev/null +++ b/insns/insn_SB.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_SB(rvfi_insn): + def __init__(self): + super(rvfi_insn_SB, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_SB, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_SB, self).elaborate(platform) + + # SB-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From c17ccdf897b78836b8a64c7ef01b87780489f43f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:28:01 +0800 Subject: [PATCH 50/84] Add BEQ instruction --- insns/insn_beq.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_beq.py diff --git a/insns/insn_beq.py b/insns/insn_beq.py new file mode 100644 index 0000000..466e2a5 --- /dev/null +++ b/insns/insn_beq.py @@ -0,0 +1,21 @@ +from insn_SB import * + +class rvfi_insn_beq(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_beq, self).__init__() + def ports(self): + return super(rvfi_insn_beq, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_beq, self).elaborate(platform) + + cond = Signal(1) + m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From 486c77a108f7b67ff7d1e529b30d0c705a076538 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:29:17 +0800 Subject: [PATCH 51/84] Fix BEQ instruction --- insns/insn_beq.py | 1 + 1 file changed, 1 insertion(+) diff --git a/insns/insn_beq.py b/insns/insn_beq.py index 466e2a5..582a331 100644 --- a/insns/insn_beq.py +++ b/insns/insn_beq.py @@ -8,6 +8,7 @@ class rvfi_insn_beq(rvfi_insn_SB): def elaborate(self, platform): m = super(rvfi_insn_beq, self).elaborate(platform) + # BEQ instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) next_pc = Signal(32) From 680042b9ee38e36bc322d64e762e8d6f7de027f7 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:33:45 +0800 Subject: [PATCH 52/84] ADD BNE instruction --- insns/insn_bne.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 insns/insn_bne.py diff --git a/insns/insn_bne.py b/insns/insn_bne.py new file mode 100644 index 0000000..6c273f0 --- /dev/null +++ b/insns/insn_bne.py @@ -0,0 +1,22 @@ +from insn_SB import * + +class rvfi_insn_bne(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bne, self).__init__() + def ports(self): + return super(rvfi_insn_bne, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_bne, self).elaborate(platform) + + # BNE instruction + cond = Signal(1) + m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From 8d1b070a0279f23789ad5347553ba89dcd9e98ec Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:38:54 +0800 Subject: [PATCH 53/84] Add BLT instruction --- insns/insn_blt.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 insns/insn_blt.py diff --git a/insns/insn_blt.py b/insns/insn_blt.py new file mode 100644 index 0000000..471f032 --- /dev/null +++ b/insns/insn_blt.py @@ -0,0 +1,22 @@ +from insn_SB import * + +class rvfi_insn_blt(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_blt, self).__init__() + def ports(self): + return super(rvfi_insn_blt, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_blt, self).elaborate(platform) + + # BLT instruction + cond = Signal(1) + m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From f6008f309631585c36140bb28f0dba01bfff53f5 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:42:27 +0800 Subject: [PATCH 54/84] Add BGE instruction --- insns/insn_bge.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 insns/insn_bge.py diff --git a/insns/insn_bge.py b/insns/insn_bge.py new file mode 100644 index 0000000..3309baa --- /dev/null +++ b/insns/insn_bge.py @@ -0,0 +1,22 @@ +from insn_SB import * + +class rvfi_insn_bge(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bge, self).__init__() + def ports(self): + return super(rvfi_insn_bge, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_bge, self).elaborate(platform) + + # BGE instruction + cond = Signal(1) + m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From 596d7fcf6dff9da7478c4dc5133bdc736a9629f9 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 11:30:16 +0800 Subject: [PATCH 55/84] Add BLTU instruction --- insns/insn_bltu.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 insns/insn_bltu.py diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py new file mode 100644 index 0000000..16dd557 --- /dev/null +++ b/insns/insn_bltu.py @@ -0,0 +1,22 @@ +from insn_SB import * + +class rvfi_insn_bltu(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bltu, self).__init__() + def ports(self): + return super(rvfi_insn_bltu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_bltu, self).elaborate(platform) + + # BLTU instruction + cond = Signal(1) + m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From 62ae797737f817282c99670095e818b36a6c7e5f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 11:33:57 +0800 Subject: [PATCH 56/84] Add BGEU instruction --- insns/insn_bgeu.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 insns/insn_bgeu.py diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py new file mode 100644 index 0000000..049be95 --- /dev/null +++ b/insns/insn_bgeu.py @@ -0,0 +1,22 @@ +from insn_SB import * + +class rvfi_insn_bgeu(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bgeu, self).__init__() + def ports(self): + return super(rvfi_insn_bgeu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_bgeu, self).elaborate(platform) + + # BGEU instruction + cond = Signal(1) + m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m From eebb39ee27c85e69f31fdf24f50b8bf03360f21e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:15:09 +0800 Subject: [PATCH 57/84] Add S-type instruction format --- insns/insn_S.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 insns/insn_S.py diff --git a/insns/insn_S.py b/insns/insn_S.py new file mode 100644 index 0000000..b757fbf --- /dev/null +++ b/insns/insn_S.py @@ -0,0 +1,32 @@ +from insn import * +class rvfi_insn_S(rvfi_insn): + def __init__(self): + super(rvfi_insn_S, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_S, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_S, self).elaborate(platform) + + # S-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + + return m From 84454e7048ede3bc88b33b0a55c48e1ff7aaf20f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:23:40 +0800 Subject: [PATCH 58/84] Add SB instruction --- insns/insn_sb.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sb.py diff --git a/insns/insn_sb.py b/insns/insn_sb.py new file mode 100644 index 0000000..a423dc4 --- /dev/null +++ b/insns/insn_sb.py @@ -0,0 +1,23 @@ +from insn_S import * + +class rvfi_insn_sb(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sb, self).__init__() + def ports(self): + return super(rvfi_insn_sb, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sb, self).elaborate(platform) + + # SB instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) + m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From 948a3db1c1bfbb7fe62a77ad6937b99a3bb7bcc5 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:27:08 +0800 Subject: [PATCH 59/84] Add SH instruction --- insns/insn_sh.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sh.py diff --git a/insns/insn_sh.py b/insns/insn_sh.py new file mode 100644 index 0000000..1a246c5 --- /dev/null +++ b/insns/insn_sh.py @@ -0,0 +1,23 @@ +from insn_S import * + +class rvfi_insn_sh(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sh, self).__init__() + def ports(self): + return super(rvfi_insn_sh, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sh, self).elaborate(platform) + + # SH instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) + m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From c3821bc8852143d67e4daa6ad88dc690ce8827d1 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:29:52 +0800 Subject: [PATCH 60/84] Add SW instruction --- insns/insn_sw.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sw.py diff --git a/insns/insn_sw.py b/insns/insn_sw.py new file mode 100644 index 0000000..cb02983 --- /dev/null +++ b/insns/insn_sw.py @@ -0,0 +1,23 @@ +from insn_S import * + +class rvfi_insn_sw(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sw, self).__init__() + def ports(self): + return super(rvfi_insn_sw, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sw, self).elaborate(platform) + + # SW instruction + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_mem_addr.eq(addr) + m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) + m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + + return m From a9cff77a82285958ca35eba1616381422e43bdef Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:44:33 +0800 Subject: [PATCH 61/84] Add I-type (shift variation) instruction format --- insns/insn_I_shift.py | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/insn_I_shift.py diff --git a/insns/insn_I_shift.py b/insns/insn_I_shift.py new file mode 100644 index 0000000..45f2819 --- /dev/null +++ b/insns/insn_I_shift.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_I_shift(rvfi_insn): + def __init__(self): + super(rvfi_insn_I_shift, self).__init__() + self.insn_padding = Signal(32) + self.insn_funct6 = Signal(7) + self.insn_shamt = Signal(6) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_I_shift, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I_shift, self).elaborate(platform) + + # I-type instruction format (shift variation) + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) + m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From 0234b658902b8d231b2a2863e7be6da9cf2f0072 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:51:36 +0800 Subject: [PATCH 62/84] Add SLLI instruction --- insns/insn_slli.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_slli.py diff --git a/insns/insn_slli.py b/insns/insn_slli.py new file mode 100644 index 0000000..6d18539 --- /dev/null +++ b/insns/insn_slli.py @@ -0,0 +1,20 @@ +from insn_I_shift import * + +class rvfi_insn_slli(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_slli, self).__init__() + def ports(self): + return super(rvfi_insn_slli, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_slli, self).elaborate(platform) + + # SLLI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From eaf475ee04b895345a4fb65582d27ac500224c97 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:54:02 +0800 Subject: [PATCH 63/84] Add SRLI instruction --- insns/insn_srli.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_srli.py diff --git a/insns/insn_srli.py b/insns/insn_srli.py new file mode 100644 index 0000000..f239860 --- /dev/null +++ b/insns/insn_srli.py @@ -0,0 +1,20 @@ +from insn_I_shift import * + +class rvfi_insn_srli(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_srli, self).__init__() + def ports(self): + return super(rvfi_insn_srli, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_srli, self).elaborate(platform) + + # SRLI instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata >> self.insn_shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 19099edee3a35b042e6a47febf626bc5d9f9c4d4 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 15:10:58 +0800 Subject: [PATCH 64/84] Add SRAI instruction --- insns/insn_srai.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_srai.py diff --git a/insns/insn_srai.py b/insns/insn_srai.py new file mode 100644 index 0000000..ad17861 --- /dev/null +++ b/insns/insn_srai.py @@ -0,0 +1,20 @@ +from insn_I_shift import * + +class rvfi_insn_srai(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_srai, self).__init__() + def ports(self): + return super(rvfi_insn_srai, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_srai, self).elaborate(platform) + + # SRAI instruction + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata >> self.insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - self.insn_shamt))) # https://stackoverflow.com/a/25207042 + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b010000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 3abdcf07d2c35a52a621baba880f3fae5f2ffb91 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:06:01 +0800 Subject: [PATCH 65/84] Add R-type instruction format --- insns/insn_R.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 insns/insn_R.py diff --git a/insns/insn_R.py b/insns/insn_R.py new file mode 100644 index 0000000..8fb73fb --- /dev/null +++ b/insns/insn_R.py @@ -0,0 +1,37 @@ +from insn import * + +class rvfi_insn_R(rvfi_insn): + def __init__(self): + super(rvfi_insn_R, self).__init__() + self.insn_padding = Signal(32) + self.insn_funct7 = Signal(7) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_R, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_R, self).elaborate(platform) + + # R-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32]) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m From aad9a3f2b57db0b5b5dc949eb1ad128106ebea4b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:20:52 +0800 Subject: [PATCH 66/84] Add ADD instruction --- insns/insn_add.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_add.py diff --git a/insns/insn_add.py b/insns/insn_add.py new file mode 100644 index 0000000..58a9300 --- /dev/null +++ b/insns/insn_add.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_add(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_add, self).__init__() + def ports(self): + return super(rvfi_insn_add, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_add, self).elaborate(platform) + + # ADD instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 67c57c4d7d0147a1a37e27fe53333d08485adf12 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:25:12 +0800 Subject: [PATCH 67/84] Add SUB instruction --- insns/insn_sub.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_sub.py diff --git a/insns/insn_sub.py b/insns/insn_sub.py new file mode 100644 index 0000000..20c394a --- /dev/null +++ b/insns/insn_sub.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_sub(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sub, self).__init__() + def ports(self): + return super(rvfi_insn_sub, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sub, self).elaborate(platform) + + # SUB instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From a6a09ac1209048d7b048574e34f8aca990a7f480 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:31:36 +0800 Subject: [PATCH 68/84] Add SLL instruction --- insns/insn_sll.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sll.py diff --git a/insns/insn_sll.py b/insns/insn_sll.py new file mode 100644 index 0000000..5158983 --- /dev/null +++ b/insns/insn_sll.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_sll(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sll, self).__init__() + def ports(self): + return super(rvfi_insn_sll, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sll, self).elaborate(platform) + + # SLL instruction + shamt = Signal(6) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 4d313ed54add8078110e7e1644ceb35d8b806d3f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:34:06 +0800 Subject: [PATCH 69/84] Add SLT instruction --- insns/insn_slt.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_slt.py diff --git a/insns/insn_slt.py b/insns/insn_slt.py new file mode 100644 index 0000000..667255c --- /dev/null +++ b/insns/insn_slt.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_slt(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_slt, self).__init__() + def ports(self): + return super(rvfi_insn_slt, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_slt, self).elaborate(platform) + + # SLT instruction + result = Signal(32) + m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From cf9e1c741c621ceb4e057f28f7fbb8dee1c729ce Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:37:26 +0800 Subject: [PATCH 70/84] Add SLTU instruction --- insns/insn_sltu.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_sltu.py diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py new file mode 100644 index 0000000..4f45aa4 --- /dev/null +++ b/insns/insn_sltu.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_sltu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sltu, self).__init__() + def ports(self): + return super(rvfi_insn_sltu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sltu, self).elaborate(platform) + + # SLTU instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 0c7c92998365f80ed68ba7fdf289792ec5b219d3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:39:20 +0800 Subject: [PATCH 71/84] Add XOR instruction --- insns/insn_xor.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_xor.py diff --git a/insns/insn_xor.py b/insns/insn_xor.py new file mode 100644 index 0000000..c332429 --- /dev/null +++ b/insns/insn_xor.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_xor(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_xor, self).__init__() + def ports(self): + return super(rvfi_insn_xor, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_xor, self).elaborate(platform) + + # XOR instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 907f7240bfe3779b3bea0ebfd784ff976a9b30dc Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:42:39 +0800 Subject: [PATCH 72/84] Add SRL instruction --- insns/insn_srl.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_srl.py diff --git a/insns/insn_srl.py b/insns/insn_srl.py new file mode 100644 index 0000000..a03f8f1 --- /dev/null +++ b/insns/insn_srl.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_srl(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_srl, self).__init__() + def ports(self): + return super(rvfi_insn_srl, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_srl, self).elaborate(platform) + + # SRL instruction + shamt = Signal(6) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From a3a9592c194896b47e28203e10ee3568ffb49144 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:47:35 +0800 Subject: [PATCH 73/84] Add SRA instruction --- insns/insn_sra.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sra.py diff --git a/insns/insn_sra.py b/insns/insn_sra.py new file mode 100644 index 0000000..c3075d9 --- /dev/null +++ b/insns/insn_sra.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_sra(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sra, self).__init__() + def ports(self): + return super(rvfi_insn_sra, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sra, self).elaborate(platform) + + # SRA instruction + shamt = Signal(6) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042 + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 942940361699246bca43793bc8de7ab4a99af24b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:51:48 +0800 Subject: [PATCH 74/84] Add OR instruction --- insns/insn_or.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_or.py diff --git a/insns/insn_or.py b/insns/insn_or.py new file mode 100644 index 0000000..ad09251 --- /dev/null +++ b/insns/insn_or.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_or(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_or, self).__init__() + def ports(self): + return super(rvfi_insn_or, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_or, self).elaborate(platform) + + # OR instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From aa47b866a159a0532746c78bfecc97355eab364c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:54:46 +0800 Subject: [PATCH 75/84] Add AND instruction --- insns/insn_and.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_and.py diff --git a/insns/insn_and.py b/insns/insn_and.py new file mode 100644 index 0000000..4cf5a52 --- /dev/null +++ b/insns/insn_and.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_and(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_and, self).__init__() + def ports(self): + return super(rvfi_insn_and, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_and, self).elaborate(platform) + + # AND instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From e1bbf567c22c9083febf0c44d5816881a33796c2 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 16:57:43 +0800 Subject: [PATCH 76/84] Add MUL instruction --- insns/insn_mul.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_mul.py diff --git a/insns/insn_mul.py b/insns/insn_mul.py new file mode 100644 index 0000000..5f250b1 --- /dev/null +++ b/insns/insn_mul.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_mul(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mul, self).__init__() + def ports(self): + return super(rvfi_insn_mul, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_mul, self).elaborate(platform) + + # MUL instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From a26813835f8ac8ab74e6dce697c4abc40c0fedd3 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:00:43 +0800 Subject: [PATCH 77/84] Add MULH instruction --- insns/insn_mulh.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_mulh.py diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py new file mode 100644 index 0000000..81010c2 --- /dev/null +++ b/insns/insn_mulh.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_mulh(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulh, self).__init__() + def ports(self): + return super(rvfi_insn_mulh, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_mulh, self).elaborate(platform) + + # MULH instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From ee38e3a61d69fbfef244f41d97d5ebe492f8e595 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:04:04 +0800 Subject: [PATCH 78/84] Add MULHSU instruction --- insns/insn_mulhsu.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_mulhsu.py diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py new file mode 100644 index 0000000..18857d8 --- /dev/null +++ b/insns/insn_mulhsu.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_mulhsu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulhsu, self).__init__() + def ports(self): + return super(rvfi_insn_mulhsu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_mulhsu, self).elaborate(platform) + + # MULHSU instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 7b39ce135fe6eb49018758ca065a627ce18b5ab1 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:06:49 +0800 Subject: [PATCH 79/84] Add MULHU instruction --- insns/insn_mulhu.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_mulhu.py diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py new file mode 100644 index 0000000..efeaed4 --- /dev/null +++ b/insns/insn_mulhu.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_mulhu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulhu, self).__init__() + def ports(self): + return super(rvfi_insn_mulhu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_mulhu, self).elaborate(platform) + + # MULHU instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 2a809073a566ba9ac666d23c14fb1082b520aacf Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:09:21 +0800 Subject: [PATCH 80/84] Add DIV instruction --- insns/insn_div.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_div.py diff --git a/insns/insn_div.py b/insns/insn_div.py new file mode 100644 index 0000000..2cd2523 --- /dev/null +++ b/insns/insn_div.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_div(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_div, self).__init__() + def ports(self): + return super(rvfi_insn_div, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_div, self).elaborate(platform) + + # DIV instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 78fb149761885f0f207b697f297bf38f1f624c2e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:12:13 +0800 Subject: [PATCH 81/84] Add DIVU instruction --- insns/insn_divu.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_divu.py diff --git a/insns/insn_divu.py b/insns/insn_divu.py new file mode 100644 index 0000000..454eb00 --- /dev/null +++ b/insns/insn_divu.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_divu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_divu, self).__init__() + def ports(self): + return super(rvfi_insn_divu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_divu, self).elaborate(platform) + + # DIVU instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From af8704cea03baa30a06b74b4b98903645dea0232 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:14:46 +0800 Subject: [PATCH 82/84] Add REM instruction --- insns/insn_rem.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_rem.py diff --git a/insns/insn_rem.py b/insns/insn_rem.py new file mode 100644 index 0000000..b2efb57 --- /dev/null +++ b/insns/insn_rem.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_rem(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_rem, self).__init__() + def ports(self): + return super(rvfi_insn_rem, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_rem, self).elaborate(platform) + + # REM instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From c4e30e9c550aca6eb1668a91eea750b6f87f6f4c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 17:17:37 +0800 Subject: [PATCH 83/84] Add REMU instruction --- insns/insn_remu.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_remu.py diff --git a/insns/insn_remu.py b/insns/insn_remu.py new file mode 100644 index 0000000..eb50e4d --- /dev/null +++ b/insns/insn_remu.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_remu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_remu, self).__init__() + def ports(self): + return super(rvfi_insn_remu, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_remu, self).elaborate(platform) + + # REMU instruction + altops_bitmask = Signal(32) + m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m From 7c60451bfaf8b120019f991edd75e56e2d07db37 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 5 Aug 2020 12:54:46 +0800 Subject: [PATCH 84/84] Add README for instructions --- README.md | 2 +- insns/README.md | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 insns/README.md diff --git a/README.md b/README.md index 271ce33..e08822d 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen TODO -## Support +## Scope The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future. diff --git a/insns/README.md b/insns/README.md new file mode 100644 index 0000000..034ebc4 --- /dev/null +++ b/insns/README.md @@ -0,0 +1,28 @@ +# RISC-V Instructions + +Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*. + +| Instruction type | Instructions | +| --- | --- | +| U-type | lui, auipc | +| UJ-type | jal | +| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | +| SB-type | beq, bne, blt, bge, bltu, bgeu | +| S-type | sb, sh, sw | +| I-type (shift variation) | slli, srli, srai | +| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | + +\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks. + +## Caveats + +At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation: + +| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen | +| --- | --- | +| `RISCV_FORMAL_ILEN` | 32 | +| `RISCV_FORMAL_XLEN` | 32 | +| `RISCV_FORMAL_CSR_MISA` | undefined | +| `RISCV_FORMAL_COMPRESSED` | undefined | +| `RISCV_FORMAL_ALIGNED_MEM` | undefined | +| `RISCV_FORMAL_ALTOPS` | defined |