diff --git a/README.md b/README.md index 271ce33..e08822d 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen TODO -## Support +## Scope The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future. diff --git a/insns/README.md b/insns/README.md new file mode 100644 index 0000000..034ebc4 --- /dev/null +++ b/insns/README.md @@ -0,0 +1,28 @@ +# RISC-V Instructions + +Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*. + +| Instruction type | Instructions | +| --- | --- | +| U-type | lui, auipc | +| UJ-type | jal | +| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | +| SB-type | beq, bne, blt, bge, bltu, bgeu | +| S-type | sb, sh, sw | +| I-type (shift variation) | slli, srli, srai | +| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | + +\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks. + +## Caveats + +At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation: + +| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen | +| --- | --- | +| `RISCV_FORMAL_ILEN` | 32 | +| `RISCV_FORMAL_XLEN` | 32 | +| `RISCV_FORMAL_CSR_MISA` | undefined | +| `RISCV_FORMAL_COMPRESSED` | undefined | +| `RISCV_FORMAL_ALIGNED_MEM` | undefined | +| `RISCV_FORMAL_ALTOPS` | defined | diff --git a/insns/insn.py b/insns/insn.py new file mode 100644 index 0000000..4588ff3 --- /dev/null +++ b/insns/insn.py @@ -0,0 +1,51 @@ +from nmigen import * + +class rvfi_insn(Elaboratable): + def __init__(self): + # Input ports + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(32) + self.rvfi_pc_rdata = Signal(32) + self.rvfi_rs1_rdata = Signal(32) + self.rvfi_rs2_rdata = Signal(32) + self.rvfi_mem_rdata = Signal(32) + + # Output ports + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(32) + self.spec_pc_wdata = Signal(32) + self.spec_mem_addr = Signal(32) + self.spec_mem_rmask = Signal(4) + self.spec_mem_wmask = Signal(4) + self.spec_mem_wdata = Signal(32) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + return input_ports + output_ports + def elaborate(self, platform): + m = Module() + + return m diff --git a/insns/insn_I.py b/insns/insn_I.py new file mode 100644 index 0000000..3d0c7e3 --- /dev/null +++ b/insns/insn_I.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_I(rvfi_insn): + def __init__(self): + super(rvfi_insn_I, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_I, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I, self).elaborate(platform) + + # I-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_I_shift.py b/insns/insn_I_shift.py new file mode 100644 index 0000000..45f2819 --- /dev/null +++ b/insns/insn_I_shift.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_I_shift(rvfi_insn): + def __init__(self): + super(rvfi_insn_I_shift, self).__init__() + self.insn_padding = Signal(32) + self.insn_funct6 = Signal(7) + self.insn_shamt = Signal(6) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_I_shift, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I_shift, self).elaborate(platform) + + # I-type instruction format (shift variation) + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) + m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_R.py b/insns/insn_R.py new file mode 100644 index 0000000..8fb73fb --- /dev/null +++ b/insns/insn_R.py @@ -0,0 +1,37 @@ +from insn import * + +class rvfi_insn_R(rvfi_insn): + def __init__(self): + super(rvfi_insn_R, self).__init__() + self.insn_padding = Signal(32) + self.insn_funct7 = Signal(7) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_R, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_R, self).elaborate(platform) + + # R-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct7.eq(self.rvfi_insn[25:32]) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_S.py b/insns/insn_S.py new file mode 100644 index 0000000..b757fbf --- /dev/null +++ b/insns/insn_S.py @@ -0,0 +1,32 @@ +from insn import * +class rvfi_insn_S(rvfi_insn): + def __init__(self): + super(rvfi_insn_S, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_S, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_S, self).elaborate(platform) + + # S-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + + return m diff --git a/insns/insn_SB.py b/insns/insn_SB.py new file mode 100644 index 0000000..352f0c6 --- /dev/null +++ b/insns/insn_SB.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_SB(rvfi_insn): + def __init__(self): + super(rvfi_insn_SB, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_SB, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_SB, self).elaborate(platform) + + # SB-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_U.py b/insns/insn_U.py new file mode 100644 index 0000000..aec6828 --- /dev/null +++ b/insns/insn_U.py @@ -0,0 +1,33 @@ +from insn import * + +class rvfi_insn_U(rvfi_insn): + def __init__(self): + super(rvfi_insn_U, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_U, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_U, self).elaborate(platform) + + # U-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # Default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_UJ.py b/insns/insn_UJ.py new file mode 100644 index 0000000..d5d2b8f --- /dev/null +++ b/insns/insn_UJ.py @@ -0,0 +1,34 @@ +from insn import * + +class rvfi_insn_UJ(rvfi_insn): + def __init__(self): + super(rvfi_insn_UJ, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_UJ, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_UJ, self).elaborate(platform) + + # UJ-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # Default assignments + m.d.comb += self.spec_rs1_addr.eq(0) + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m diff --git a/insns/insn_add.py b/insns/insn_add.py index d995dff..58a9300 100644 --- a/insns/insn_add.py +++ b/insns/insn_add.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_add(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_add(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_add, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_add, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_add, self).elaborate(platform) # ADD instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_addi.py b/insns/insn_addi.py index 634279d..70c7537 100644 --- a/insns/insn_addi.py +++ b/insns/insn_addi.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_addi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_addi(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_addi, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_addi, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_addi, self).elaborate(platform) # ADDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_and.py b/insns/insn_and.py index e27275b..4cf5a52 100644 --- a/insns/insn_and.py +++ b/insns/insn_and.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_and(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_and(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_and, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_and, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_and, self).elaborate(platform) # AND instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_andi.py b/insns/insn_andi.py index 5f3a91d..6d4c0fa 100644 --- a/insns/insn_andi.py +++ b/insns/insn_andi.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_andi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_andi(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_andi, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_andi, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_andi, self).elaborate(platform) # ANDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata & insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata & self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py index 02f0da5..07a9f63 100644 --- a/insns/insn_auipc.py +++ b/insns/insn_auipc.py @@ -1,78 +1,17 @@ -from nmigen import * +from insn_U import * -class rvfi_insn_auipc(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_auipc(rvfi_insn_U): + def __init__(self): + super(rvfi_insn_auipc, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_auipc, self).ports() def elaborate(self, platform): - m = Module() - - # U-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_auipc, self).elaborate(platform) # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + insn_imm, 0)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py index 063241c..582a331 100644 --- a/insns/insn_beq.py +++ b/insns/insn_beq.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_beq(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_beq(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_beq, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_beq, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_beq, self).elaborate(platform) # BEQ instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_bge.py b/insns/insn_bge.py index 2f8ce08..3309baa 100644 --- a/insns/insn_bge.py +++ b/insns/insn_bge.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_bge(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_bge(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bge, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bge, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bge, self).elaborate(platform) # BGE instruction cond = Signal(1) m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b101) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py index 79472e2..049be95 100644 --- a/insns/insn_bgeu.py +++ b/insns/insn_bgeu.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_bgeu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_bgeu(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bgeu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bgeu, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bgeu, self).elaborate(platform) # BGEU instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_blt.py b/insns/insn_blt.py index e5dda37..471f032 100644 --- a/insns/insn_blt.py +++ b/insns/insn_blt.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_blt(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_blt(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_blt, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_blt, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_blt, self).elaborate(platform) # BLT instruction cond = Signal(1) m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py index 5f44e4c..16dd557 100644 --- a/insns/insn_bltu.py +++ b/insns/insn_bltu.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_bltu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_bltu(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bltu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bltu, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bltu, self).elaborate(platform) # BLTU instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_bne.py b/insns/insn_bne.py index c6b0673..6c273f0 100644 --- a/insns/insn_bne.py +++ b/insns/insn_bne.py @@ -1,88 +1,22 @@ -from nmigen import * +from insn_SB import * -class rvfi_insn_bne(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_bne(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_bne, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_bne, self).ports() def elaborate(self, platform): - m = Module() - - # SB-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_bne, self).elaborate(platform) # BNE instruction cond = Signal(1) m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_div.py b/insns/insn_div.py index 5d71a32..2cd2523 100644 --- a/insns/insn_div.py +++ b/insns/insn_div.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_div(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_div(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_div, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_div, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_div, self).elaborate(platform) # DIV instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_divu.py b/insns/insn_divu.py index c5677f6..454eb00 100644 --- a/insns/insn_divu.py +++ b/insns/insn_divu.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_divu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_divu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_divu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_divu, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_divu, self).elaborate(platform) # DIVU instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py index 2670b76..c95cb14 100644 --- a/insns/insn_jal.py +++ b/insns/insn_jal.py @@ -1,82 +1,20 @@ -from nmigen import * +from insn_UJ import * -class rvfi_insn_jal(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_jal(rvfi_insn_UJ): + def __init__(self): + super(rvfi_insn_jal, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_jal, self).ports() def elaborate(self, platform): - m = Module() - - # UJ-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_jal, self).elaborate(platform) # JAL instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + next_pc = Signal(32) + m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py index 2529e8a..56dddd0 100644 --- a/insns/insn_jalr.py +++ b/insns/insn_jalr.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_jalr(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_jalr(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_jalr, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_jalr, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - ialign16 = Signal(1) - m.d.comb += ialign16.eq(0) + m = super(rvfi_insn_jalr, self).elaborate(platform) # JALR instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + next_pc = Signal(32) + m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m diff --git a/insns/insn_lb.py b/insns/insn_lb.py index 10d2561..4c3fba6 100644 --- a/insns/insn_lb.py +++ b/insns/insn_lb.py @@ -1,86 +1,25 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_lb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lb(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lb, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lb, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lb, self).elaborate(platform) # LB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) result = Signal(8) m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b000) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py index db836ad..3961c99 100644 --- a/insns/insn_lbu.py +++ b/insns/insn_lbu.py @@ -1,86 +1,25 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_lbu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lbu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lbu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lbu, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lbu, self).elaborate(platform) # LBU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) result = Signal(8) m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b100) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_lh.py b/insns/insn_lh.py index c6a00fc..34c7f93 100644 --- a/insns/insn_lh.py +++ b/insns/insn_lh.py @@ -1,86 +1,25 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_lh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lh(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lh, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lh, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lh, self).elaborate(platform) # LH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) result = Signal(16) m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b001) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py index 0f1c722..b050668 100644 --- a/insns/insn_lhu.py +++ b/insns/insn_lhu.py @@ -1,86 +1,25 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_lhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lhu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lhu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lhu, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lhu, self).elaborate(platform) # LHU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) result = Signal(16) m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b101) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_lui.py b/insns/insn_lui.py index 870429e..42aa764 100644 --- a/insns/insn_lui.py +++ b/insns/insn_lui.py @@ -1,78 +1,17 @@ -from nmigen import * +from insn_U import * -class rvfi_insn_lui(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lui(rvfi_insn_U): + def __init__(self): + super(rvfi_insn_lui, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lui, self).ports() def elaborate(self, platform): - m = Module() - - # U-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lui, self).elaborate(platform) # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, insn_imm, 0)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_lw.py b/insns/insn_lw.py index 4507283..5e956e9 100644 --- a/insns/insn_lw.py +++ b/insns/insn_lw.py @@ -1,86 +1,25 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_lw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_lw(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_lw, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_lw, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_lw, self).elaborate(platform) # LW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) result = Signal(32) m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b010) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_mul.py b/insns/insn_mul.py index 2e45dfd..5f250b1 100644 --- a/insns/insn_mul.py +++ b/insns/insn_mul.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_mul(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_mul(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mul, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_mul, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_mul, self).elaborate(platform) # MUL instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py index 05c93b6..81010c2 100644 --- a/insns/insn_mulh.py +++ b/insns/insn_mulh.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_mulh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_mulh(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulh, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_mulh, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_mulh, self).elaborate(platform) # MULH instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py index f8e957c..18857d8 100644 --- a/insns/insn_mulhsu.py +++ b/insns/insn_mulhsu.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_mulhsu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_mulhsu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulhsu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_mulhsu, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_mulhsu, self).elaborate(platform) # MULHSU instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py index 685a6c3..efeaed4 100644 --- a/insns/insn_mulhu.py +++ b/insns/insn_mulhu.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_mulhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_mulhu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_mulhu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_mulhu, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_mulhu, self).elaborate(platform) # MULHU instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_or.py b/insns/insn_or.py index 85ca004..ad09251 100644 --- a/insns/insn_or.py +++ b/insns/insn_or.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_or(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_or(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_or, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_or, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_or, self).elaborate(platform) # OR instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_ori.py b/insns/insn_ori.py index e4f8683..3d4bb82 100644 --- a/insns/insn_ori.py +++ b/insns/insn_ori.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_ori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_ori(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_ori, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_ori, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_ori, self).elaborate(platform) # ORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata | insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata | self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_rem.py b/insns/insn_rem.py index 3feba03..b2efb57 100644 --- a/insns/insn_rem.py +++ b/insns/insn_rem.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_rem(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_rem(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_rem, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_rem, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_rem, self).elaborate(platform) # REM instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_remu.py b/insns/insn_remu.py index 068ac62..eb50e4d 100644 --- a/insns/insn_remu.py +++ b/insns/insn_remu.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_remu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_remu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_remu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_remu, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_remu, self).elaborate(platform) # REMU instruction - altops_bitmask = Signal(64) + altops_bitmask = Signal(32) m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sb.py b/insns/insn_sb.py index e7a25b6..a423dc4 100644 --- a/insns/insn_sb.py +++ b/insns/insn_sb.py @@ -1,84 +1,23 @@ -from nmigen import * +from insn_S import * -class rvfi_insn_sb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sb(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sb, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sb, self).ports() def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sb, self).elaborate(platform) # SB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_sh.py b/insns/insn_sh.py index f85446b..1a246c5 100644 --- a/insns/insn_sh.py +++ b/insns/insn_sh.py @@ -1,84 +1,23 @@ -from nmigen import * +from insn_S import * -class rvfi_insn_sh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sh(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sh, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sh, self).ports() def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sh, self).elaborate(platform) # SH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_sll.py b/insns/insn_sll.py index 08377af..5158983 100644 --- a/insns/insn_sll.py +++ b/insns/insn_sll.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_sll(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sll(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sll, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sll, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sll, self).elaborate(platform) # SLL instruction shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_slli.py b/insns/insn_slli.py index 5c6cf43..6d18539 100644 --- a/insns/insn_slli.py +++ b/insns/insn_slli.py @@ -1,86 +1,20 @@ -from nmigen import * +from insn_I_shift import * -class rvfi_insn_slli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_slli(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_slli, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_slli, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_slli, self).elaborate(platform) # SLLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata << insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata << self.insn_shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_slt.py b/insns/insn_slt.py index e3ec0e2..667255c 100644 --- a/insns/insn_slt.py +++ b/insns/insn_slt.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_slt(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_slt(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_slt, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_slt, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_slt, self).elaborate(platform) # SLT instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_slti.py b/insns/insn_slti.py index 01e2863..a84f502 100644 --- a/insns/insn_slti.py +++ b/insns/insn_slti.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_slti(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_slti(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_slti, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_slti, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_slti, self).elaborate(platform) # SLTI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(insn_imm)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py index 2f1a005..717dfef 100644 --- a/insns/insn_sltiu.py +++ b/insns/insn_sltiu.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_sltiu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sltiu(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_sltiu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sltiu, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sltiu, self).elaborate(platform) # SLTIU instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata < insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b011) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py index 810f4e7..4f45aa4 100644 --- a/insns/insn_sltu.py +++ b/insns/insn_sltu.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_sltu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sltu(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sltu, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sltu, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sltu, self).elaborate(platform) # SLTU instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sra.py b/insns/insn_sra.py index a3c3d04..c3075d9 100644 --- a/insns/insn_sra.py +++ b/insns/insn_sra.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_sra(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sra(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sra, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sra, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sra, self).elaborate(platform) # SRA instruction shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042 + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_srai.py b/insns/insn_srai.py index a9c4efb..ad17861 100644 --- a/insns/insn_srai.py +++ b/insns/insn_srai.py @@ -1,86 +1,20 @@ -from nmigen import * +from insn_I_shift import * -class rvfi_insn_srai(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_srai(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_srai, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_srai, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_srai, self).elaborate(platform) # SRAI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - insn_shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b010000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq((self.rvfi_rs1_rdata >> self.insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - self.insn_shamt))) # https://stackoverflow.com/a/25207042 + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b010000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_srl.py b/insns/insn_srl.py index e72766a..a03f8f1 100644 --- a/insns/insn_srl.py +++ b/insns/insn_srl.py @@ -1,88 +1,23 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_srl(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_srl(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_srl, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_srl, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_srl, self).elaborate(platform) # SRL instruction shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_srli.py b/insns/insn_srli.py index d8fdc27..f239860 100644 --- a/insns/insn_srli.py +++ b/insns/insn_srli.py @@ -1,86 +1,20 @@ -from nmigen import * +from insn_I_shift import * -class rvfi_insn_srli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_srli(rvfi_insn_I_shift): + def __init__(self): + super(rvfi_insn_srli, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_srli, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_srli, self).elaborate(platform) # SRLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata >> self.insn_shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == 0b000000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0010011) & (~self.insn_shamt[5])) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sub.py b/insns/insn_sub.py index a1dc233..20c394a 100644 --- a/insns/insn_sub.py +++ b/insns/insn_sub.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_sub(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sub(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sub, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sub, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sub, self).elaborate(platform) # SUB instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_sw.py b/insns/insn_sw.py index e96ec3f..cb02983 100644 --- a/insns/insn_sw.py +++ b/insns/insn_sw.py @@ -1,84 +1,23 @@ -from nmigen import * +from insn_S import * -class rvfi_insn_sw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_sw(rvfi_insn_S): + def __init__(self): + super(rvfi_insn_sw, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_sw, self).ports() def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_sw, self).elaborate(platform) # SW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) + addr = Signal(32) + m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) m.d.comb += self.spec_mem_addr.eq(addr) m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) return m diff --git a/insns/insn_types.md b/insns/insn_types.md new file mode 100644 index 0000000..5228a1f --- /dev/null +++ b/insns/insn_types.md @@ -0,0 +1,11 @@ +# RV32IM Instruction Types + +| Instruction type | Instructions | +| --- | --- | +| U-type | lui, auipc | +| UJ-type | jal | +| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi | +| SB-type | beq, bne, blt, bge, bltu, bgeu | +| S-type | sb, sh, sw | +| I-type (shift variation) | slli, srli, srai | +| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu | diff --git a/insns/insn_xor.py b/insns/insn_xor.py index a713d20..c332429 100644 --- a/insns/insn_xor.py +++ b/insns/insn_xor.py @@ -1,86 +1,21 @@ -from nmigen import * +from insn_R import * -class rvfi_insn_xor(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_xor(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_xor, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_xor, self).ports() def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_xor, self).elaborate(platform) # XOR instruction - result = Signal(self.RISCV_FORMAL_XLEN) + result = Signal(32) m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m diff --git a/insns/insn_xori.py b/insns/insn_xori.py index 19c69e0..647067d 100644 --- a/insns/insn_xori.py +++ b/insns/insn_xori.py @@ -1,84 +1,20 @@ -from nmigen import * +from insn_I import * -class rvfi_insn_xori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) +class rvfi_insn_xori(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_xori, self).__init__() def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports + return super(rvfi_insn_xori, self).ports() def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) + m = super(rvfi_insn_xori, self).elaborate(platform) # XORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.insn_imm) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0010011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - return m