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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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dsleung 1d315b4735 Merge pull request 'Refactor supported instructions to improve code reuse' (#1) from feature/refactor-insns into master 
Merging since the current state of `insns/` is a clear improvement over the previous state in terms of maintainability and code duplication, though further refactoring is required which will happen in the next pull request.
 		2020-08-06 09:47:30 +08:00
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README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Dependencies

Build

TODO

Scope

The full RISC-V specification is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.

License

See LICENSE