riscv-formal-nmigen/rvfi/insns/insn_srliw.py

from .insn_rv64i_i_type_shift import *

"""
SRLIW instruction
"""

class InsnSrliw(InsnRV64IITypeShift):
    def __init__(self, params):
        super().__init__(params, 0b000000, 0b101)

    def elaborate(self, platform):
        m = super().elaborate(platform)

        result = Signal(32)
        m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] >> self.insn_shamt)
        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))

        return m