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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

File/Directory Description
shell.nix nix-shell configuration file
rvfi RISC-V Formal Verification Framework (nMigen port)
rvfi/insns Supported RISC-V instructions and ISAs
rvfi/checks Checks for RISC-V compliant cores
rvfi/cores Cores currently tested against this port of riscv-formal
rvfi/cores/minerva/verify.py Verification tasks for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

Scope

The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM are being tested by integrating with the Minerva core.

Possible improvements

In no particular order:

  • Allow configurable limit for no. of running processes in order to prevent thrashing
  • Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only 20)

License

See LICENSE