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7665a23896
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scpi: introduce master clock setup
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2020-09-07 14:07:39 +08:00 |
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60c8215059
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hal: upgrade to 0.7.1
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2020-09-07 14:05:13 +08:00 |
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c740386d6b
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scpi: add macro for command struct
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2020-09-04 17:52:37 +08:00 |
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148f1c7a4e
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scpi: customise scpi tree macro
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2020-09-04 17:02:05 +08:00 |
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56cb6eb3fd
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scpi: redesign sw
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2020-09-04 13:29:50 +08:00 |
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37b7cc71b7
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scpi: add switch ctrl command
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2020-09-03 17:41:27 +08:00 |
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9a42674bf9
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nal: use minimq example
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2020-09-01 17:41:40 +08:00 |
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13bf8b6080
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nal-client: init
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2020-09-01 14:50:49 +08:00 |
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1e7fd93835
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scpi: fix dds test sdio_in_only
|
2020-09-01 10:21:55 +08:00 |
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8dbf621679
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scpi: implement tst
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2020-08-31 17:43:15 +08:00 |
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f60ec09b29
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scpi: implement rst
|
2020-08-31 16:48:21 +08:00 |
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d78f85721f
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ethernet: minimal impl for urukul as scpi device
|
2020-08-31 13:32:08 +08:00 |
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b0272a6fc2
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urukul: add commented code, but with lifetime conflict
|
2020-08-31 12:32:39 +08:00 |
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49594dfb3b
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urukul: very bad constructor
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2020-08-31 11:36:05 +08:00 |
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69761c4517
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cpld: fix indent
|
2020-08-31 09:34:38 +08:00 |
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4852fc54ea
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cpld: detach from lib.rs
|
2020-08-31 09:31:56 +08:00 |
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f92b2ba6f5
|
ethernet: add scpi to silent socket example
|
2020-08-28 15:48:13 +08:00 |
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fa117c94bb
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ethernet: separate pin dec
|
2020-08-27 17:09:35 +08:00 |
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fbed41ebd3
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dds: exclude RAM from impl_reg_io macro
|
2020-08-27 12:17:53 +08:00 |
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1de13d6f3a
|
dds: fix full amplitude scale
|
2020-08-27 11:15:42 +08:00 |
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|
649b5b498b
|
dds: add single tone control
|
2020-08-26 17:39:33 +08:00 |
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1d3ced0d16
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dds: add clock control
|
2020-08-26 16:49:37 +08:00 |
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|
38b1c7528c
|
dds: add register io
|
2020-08-26 13:18:50 +08:00 |
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|
990fc075f1
|
cpld: add size_of
|
2020-08-26 11:04:39 +08:00 |
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5f874e81b5
|
bitmask: add mask merging
|
2020-08-26 11:04:08 +08:00 |
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|
181ef5c72a
|
attenuator: fix reverse data
|
2020-08-25 12:20:24 +08:00 |
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|
|
29abca72cd
|
cpld: auto invoke io update
|
2020-08-24 17:03:44 +08:00 |
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|
9ec5698f63
|
migen: replace ethernet conflict pin
|
2020-08-24 10:57:37 +08:00 |
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|
6ef122c9a1
|
migen: beaufity eem res struct
|
2020-08-23 17:17:09 +08:00 |
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|
|
dbea9aba30
|
attenuator: fix return data
|
2020-08-21 14:18:33 +08:00 |
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|
|
6e6e500f8a
|
spi_slave: auto deselect chip
|
2020-08-18 15:25:32 +08:00 |
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|
|
8547610661
|
dds: add register io
|
2020-08-17 12:15:11 +08:00 |
|
|
|
afe00402b7
|
dds: add register macro
|
2020-08-17 11:45:42 +08:00 |
|
|
|
f32de647d3
|
dds: add all cfg enum
|
2020-08-14 14:14:14 +08:00 |
|
|
|
bb1feb65f7
|
dds: add cfg1 enum
|
2020-08-13 17:17:21 +08:00 |
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|
|
495bf21575
|
bitmask_macro: separated from cfg_reg
|
2020-08-13 16:51:08 +08:00 |
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|
|
31b84bc12d
|
cfg_reg: mv bitmask operation to macro
|
2020-08-13 16:31:27 +08:00 |
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|
|
fe47cafb93
|
dds: init
|
2020-08-12 15:31:06 +08:00 |
|
|
|
765cd1d513
|
cfg_reg: split enum into status and cfg
|
2020-08-12 12:28:33 +08:00 |
|
|
|
ccd6a1faf9
|
cfg_reg: add status getter
|
2020-08-12 12:26:15 +08:00 |
|
|
|
8f4a97c97e
|
cfg_reg: add getter function
|
2020-08-12 12:00:11 +08:00 |
|
|
|
0543e98956
|
cfg_reg: add setter function
|
2020-08-12 11:50:24 +08:00 |
|
|
|
e75c3d3342
|
cfg_reg: reorganize bitmasks
|
2020-08-11 16:55:31 +08:00 |
|
|
|
0df7ff71cf
|
cfg_reg: add bitmask macro
|
2020-08-11 16:51:17 +08:00 |
|
|
|
4596dc29cb
|
generic_spi_dev: removed
|
2020-08-11 11:32:10 +08:00 |
|
|
|
a1a10d7afe
|
cfg_reg: init
|
2020-08-11 11:29:47 +08:00 |
|
|
|
00938bcb23
|
attenuator: init
|
2020-08-11 00:07:07 +08:00 |
|
|
|
2def3ed95d
|
rust: changed crate structure
|
2020-08-10 18:06:15 +08:00 |
|
|
|
429fbb7443
|
cpld: fixed unwanted mut
|
2020-08-10 17:22:46 +08:00 |
|
|
|
a406dea0c7
|
cpld: spi slave WIP
|
2020-08-10 17:04:40 +08:00 |
|
|
|
8e7fe971cb
|
cpld: add release
|
2020-08-10 00:52:05 +08:00 |
|
|
|
58e77ae671
|
cpld: basic switching capability
|
2020-08-09 18:46:06 +08:00 |
|
|
|
393138dc9a
|
migen: debug spi connection
|
2020-08-09 13:42:18 +08:00 |
|
|
|
7351a9d58a
|
rust: migrated
|
2020-08-07 13:36:00 +08:00 |
|
