ethernet: separate pin dec
parent
fbed41ebd3
commit
fa117c94bb
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@ -1,5 +1,5 @@
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[target.thumbv7em-none-eabihf]
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runner = "gdb -q -x gdb_config/fpga_config.gdb"
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runner = "gdb -q -x gdb_config/openocd.gdb"
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rustflags = [
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"-C", "link-arg=-Tlink.x",
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]
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@ -11,6 +11,7 @@ panic-halt = "0.2.0"
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cortex-m = "0.6.2"
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cortex-m-rt = "0.6.12"
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embedded-hal = "0.2.4"
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stm32h7 = {version = "0.11.0"}
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stm32h7xx-hal = {version = "0.6.0", features = [ "stm32h743v", "rt", "unproven" ] }
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stm32h7-ethernet = { version = "0.2.0", features = [ "phy_lan8742a", "stm32h743v" ] }
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smoltcp = { version = "0.6.0", default-features = false, features = [ "ethernet", "proto-ipv4", "proto-ipv6", "socket-raw" ] }
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@ -19,6 +19,8 @@ use cortex_m_rt::{
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use cortex_m_semihosting::hprintln;
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extern crate smoltcp;
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// Ethernet crate for STM32H7 has been merged into HAL in the latest commit
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extern crate stm32h7_ethernet as ethernet;
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use stm32h7xx_hal::gpio::Speed;
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@ -48,7 +50,6 @@ use core::mem::uninitialized;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::socket::SocketSet;
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//use smoltcp::socket::{UdpSocket, UdpSocketBuffer, UdpPacketMetadata};
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use smoltcp::socket::{SocketHandle, TcpSocket, TcpSocketBuffer};
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use smoltcp::time::{Duration, Instant};
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@ -132,15 +133,11 @@ fn main() -> ! {
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status_led.set_low().ok();
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listen_led.set_low().ok();
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let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_tx_en = gpiog.pg11.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_txd0 = gpiog.pg13.into_alternate_af11().set_speed(VeryHigh);
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let _rmii_txd1 = gpiob.pb13.into_alternate_af11().set_speed(VeryHigh);
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// Setup ethernet pins
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setup_ethernet_pins(
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gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7, gpioc.pc4,
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gpioc.pc5, gpiog.pg11, gpiog.pg13, gpiob.pb13
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);
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// Initialise ethernet...
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assert_eq!(ccdr.clocks.hclk().0, 200_000_000); // HCLK 200MHz
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@ -304,6 +301,32 @@ fn main() -> ! {
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}
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}
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use stm32h7xx_hal::gpio::{
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gpioa::{PA1, PA2, PA7},
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gpiob::{PB13},
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gpioc::{PC1, PC4, PC5},
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gpiog::{PG11, PG13},
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Speed::VeryHigh,
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};
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/*
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* Migrated ethernet setup pins
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*/
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pub fn setup_ethernet_pins<REF_CLK, MDIO, MDC, CRS_DV, RXD0, RXD1, TX_EN, TXD0, TXD1>(
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pa1: PA1<REF_CLK>, pa2: PA2<MDIO>, pc1: PC1<MDC>, pa7: PA7<CRS_DV>, pc4: PC4<RXD0>,
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pc5: PC5<RXD1>, pg11: PG11<TX_EN>, pg13: PG13<TXD0>, pb13: PB13<TXD1>
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) {
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pa1.into_alternate_af11().set_speed(VeryHigh);
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pa2.into_alternate_af11().set_speed(VeryHigh);
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pc1.into_alternate_af11().set_speed(VeryHigh);
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pa7.into_alternate_af11().set_speed(VeryHigh);
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pc4.into_alternate_af11().set_speed(VeryHigh);
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pc5.into_alternate_af11().set_speed(VeryHigh);
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pg11.into_alternate_af11().set_speed(VeryHigh);
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pg13.into_alternate_af11().set_speed(VeryHigh);
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pb13.into_alternate_af11().set_speed(VeryHigh);
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}
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#[interrupt]
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fn ETH() {
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unsafe { ethernet::interrupt_handler() }
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101
src/main.rs
101
src/main.rs
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@ -119,52 +119,77 @@ fn main() -> ! {
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dds0.set_configurations(&mut [
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(DDSCFRMask::PDCLK_ENABLE, 0),
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(DDSCFRMask::READ_EFFECTIVE_FTW, 1),
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(DDSCFRMask::DIGITAL_RAMP_ENABLE, 0),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 1),
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]).unwrap();
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dds0.enable_pll(1_150_000_000).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x02, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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// Calculate FTW
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let f_out = 10_000_000;
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let f_sclk = 1_150_000_000;
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let resolution :u64 = 1 << 32;
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let ftw = (resolution * f_out / f_sclk) as u32;
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// Read single-tone profile 0
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let mut profile :[u8; 8] = [0; 8];
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dds0.read_register(0x0E, &mut profile).unwrap();
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// Overwrite FTW on profile 0
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profile[0] = 0x1F;
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profile[1] = 0xFF;
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profile[4] = ((ftw >> 24) & 0xFF) as u8;
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profile[5] = ((ftw >> 16) & 0xFF) as u8;
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profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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dds0.write_register(0x0E, &mut profile).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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dds0.enable_pll(1_000_000_000).unwrap();
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// Attenuator
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att.set_attenuation([
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0.0, 31.5, 24.0, 0.0
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]).unwrap();
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hprintln!("{:#X?}", dds0.get_configurations(&mut
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[
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(DDSCFRMask::SDIO_IN_ONLY, 0),
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(DDSCFRMask::LSB_FIRST, 0),
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(DDSCFRMask::PROFILE_CTRL, 0),
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(DDSCFRMask::EN_AMP_SCALE_SINGLE_TONE_PRO, 0),
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(DDSCFRMask::DRV0, 0),
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(DDSCFRMask::VCO_SEL, 0)
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]
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).unwrap()).unwrap();
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dds0.set_single_tone_profile(1, 10_000_000, 0.0, 0.5).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 1),
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]).unwrap();
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// Setup RAM configuration
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 1),
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(DDSCFRMask::RAM_PLAYBACK_DST, 2),
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]).unwrap();
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// Configure RAM profile 0
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dds0.write_register(0x0E, &mut [
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0x00, // Open
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0x09, 0xC4, // Address step rate (2500)
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0xFF, 0xC0, // End at address 1023
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0x00, 0x00, // Start at address 0
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0x04, // Recirculate mode
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]).unwrap();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut[
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0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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]).unwrap()).unwrap();
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// Choose profile 0
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 0),
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]).unwrap();
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// Set RAM to be amplitudes, disable RAM momentarily
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_PLAYBACK_DST, 0),
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(DDSCFRMask::RAM_ENABLE, 0),
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]).unwrap();
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let mut ram_data: [u8; ((1024 * 4) + 1)] = [0; (1024 * 4) + 1];
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ram_data[0] = 0x16;
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for index in 0..1024 {
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if index % 2 == 1 {
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ram_data[(index * 4) + 1] = 0x3F;
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ram_data[(index * 4) + 2] = 0xFF;
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} else {
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ram_data[(index * 4) + 1] = 0x00;
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ram_data[(index * 4) + 2] = 0x00;
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}
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// ram_data[(index * 4) + 1] = ((index >> 2) & 0xFF) as u8;
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// ram_data[(index * 4) + 2] = ((index & 0x03) << 6) as u8;
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}
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dds0.transfer(&mut ram_data).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 1),
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]).unwrap();
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config.set_configurations(&mut [
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(CFGMask::PROFILE, 0),
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]).unwrap();
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dds0.set_configurations(&mut [
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(DDSCFRMask::RAM_ENABLE, 1),
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]).unwrap();
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loop {}
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}
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