David Leibrandt 99104499f9 gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623		2016-11-20 15:22:08 +08:00
..
amp	Implement core device storage (fixes #219).	2016-01-10 13:04:55 +00:00
rtio	rtio: do not reset DDS and SPI PHYs on RTIO reset (#503)	2016-07-09 10:07:19 +08:00
targets	gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623	2016-11-20 15:22:08 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
soc.py	soc: use add_extra_software_packages, factor builder code	2016-03-07 00:18:47 +08:00
spi.py	spi: use misoc SPIMachine, closes #314	2016-08-26 14:09:05 +02:00