mirror of https://github.com/m-labs/artiq.git
62 lines
2.3 KiB
Python
62 lines
2.3 KiB
Python
import os
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from misoc.integration.soc_core import mem_decoder
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from misoc.cores import timer
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from misoc.interconnect import wishbone
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from misoc.integration.builder import *
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from artiq.gateware import amp
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from artiq import __artiq_dir__ as artiq_dir
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class AMPSoC:
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"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs.
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Users must disable the timer from the platform SoC and provide
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a "mailbox" entry in the memory map.
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"""
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def __init__(self):
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if not hasattr(self, "cpu"):
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raise ValueError("Platform SoC must be initialized first")
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if hasattr(self, "timer0"):
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raise ValueError("Timer already exists. "
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"Initialize platform SoC using with_timer=False")
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self.submodules.timer0 = timer.Timer(width=64)
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self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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self.submodules.mailbox = amp.Mailbox()
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self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i1)
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
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self.mailbox.i2)
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self.add_memory_region("mailbox",
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self.mem_map["mailbox"] | 0x80000000, 4)
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self.submodules.timer_kernel = timer.Timer()
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self.register_kernel_cpu_csrdevice("timer_kernel")
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def register_kernel_cpu_csrdevice(self, name):
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# make sure the device is not getting connected to the comms-CPU already
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assert self.csr_map[name] is None
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csrs = getattr(self, name).get_csrs()
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bank = wishbone.CSRBank(csrs)
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self.submodules += bank
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self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
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bank.bus)
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self.add_csr_region(name,
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self.mem_map[name] | 0x80000000, 32,
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csrs)
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def build_artiq_soc(soc, argdict):
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builder = Builder(soc, **argdict)
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builder.add_extra_software_packages()
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builder.add_software_package("liblwip", os.path.join(artiq_dir, "runtime",
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"liblwip"))
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builder.add_software_package("runtime", os.path.join(artiq_dir, "runtime"))
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builder.build()
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