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spi: use misoc SPIMachine, closes #314
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commit
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@ -1,163 +1,8 @@
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from itertools import product
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from migen import *
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from migen.genlib.fsm import FSM, NextState
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from misoc.interconnect import wishbone
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class SPIClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.bias = Signal() # bias this clock phase to longer times
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self.edge = Signal()
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self.clk = Signal(reset=1)
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cnt = Signal.like(self.load)
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bias = Signal()
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zero = Signal()
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self.comb += [
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zero.eq(cnt == 0),
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self.edge.eq(zero & ~bias),
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]
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self.sync += [
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If(zero,
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bias.eq(0),
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).Else(
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cnt.eq(cnt - 1),
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),
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If(self.edge,
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cnt.eq(self.load[1:]),
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bias.eq(self.load[0] & (self.clk ^ self.bias)),
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self.clk.eq(~self.clk),
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)
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]
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class SPIRegister(Module):
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def __init__(self, width):
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self.data = Signal(width)
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self.o = Signal()
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self.i = Signal()
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self.lsb = Signal()
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self.shift = Signal()
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self.sample = Signal()
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self.comb += [
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self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
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]
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self.sync += [
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If(self.shift,
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If(self.lsb,
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self.data[:-1].eq(self.data[1:]),
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).Else(
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self.data[1:].eq(self.data[:-1]),
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)
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),
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If(self.sample,
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If(self.lsb,
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self.data[-1].eq(self.i),
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).Else(
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self.data[0].eq(self.i),
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)
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)
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]
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class SPIBitCounter(Module):
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def __init__(self, width):
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self.n_read = Signal(width)
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self.n_write = Signal(width)
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self.read = Signal()
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self.write = Signal()
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self.done = Signal()
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self.comb += [
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self.write.eq(self.n_write != 0),
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self.read.eq(self.n_read != 0),
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self.done.eq(~(self.write | self.read)),
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]
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self.sync += [
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If(self.write,
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self.n_write.eq(self.n_write - 1),
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).Elif(self.read,
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self.n_read.eq(self.n_read - 1),
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)
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]
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class SPIMachine(Module):
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def __init__(self, data_width, clock_width, bits_width):
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ce = CEInserter()
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self.submodules.cg = ce(SPIClockGen(clock_width))
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self.submodules.reg = ce(SPIRegister(data_width))
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self.submodules.bits = ce(SPIBitCounter(bits_width))
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self.div_write = Signal.like(self.cg.load)
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self.div_read = Signal.like(self.cg.load)
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self.clk_phase = Signal()
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self.start = Signal()
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self.cs = Signal()
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self.oe = Signal()
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self.done = Signal()
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# # #
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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If(self.clk_phase,
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NextState("WAIT"),
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).Else(
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NextState("SETUP"),
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)
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)
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)
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fsm.act("SETUP",
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self.reg.sample.eq(1),
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NextState("HOLD"),
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)
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fsm.act("HOLD",
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If(self.bits.done & ~self.start,
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If(self.clk_phase,
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NextState("IDLE"),
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).Else(
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NextState("WAIT"),
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)
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).Else(
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self.reg.shift.eq(~self.start),
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NextState("SETUP"),
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)
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)
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fsm.act("WAIT",
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If(self.bits.done,
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NextState("IDLE"),
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).Else(
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NextState("SETUP"),
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)
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)
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write0 = Signal()
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self.sync += [
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If(self.cg.edge & self.reg.shift,
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write0.eq(self.bits.write),
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)
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]
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self.comb += [
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self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
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If(self.bits.write | ~self.bits.read,
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self.cg.load.eq(self.div_write),
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).Else(
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self.cg.load.eq(self.div_read),
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),
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self.cg.bias.eq(self.clk_phase),
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fsm.ce.eq(self.cg.edge),
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self.cs.eq(~fsm.ongoing("IDLE")),
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self.reg.ce.eq(self.cg.edge),
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self.bits.ce.eq(self.cg.edge & self.reg.sample),
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self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
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self.oe.eq(write0 | self.bits.write),
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]
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from misoc.cores.spi.core import SPIMachine
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class SPIMaster(Module):
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