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mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 13:16:35 +08:00
artiq/artiq/gateware/rtio
2017-07-04 10:48:06 +02:00
..
phy sawg: don't enable_replace for Config 2017-06-28 20:31:40 +02:00
__init__.py rtio: export DMA and CRIInterconnectShared 2016-12-01 16:30:29 +08:00
analyzer.py make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
cdc.py drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
core.py rtio: make pipelined logic reset_less 2017-06-29 12:55:32 +02:00
cri.py cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
dma.py artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
moninj.py moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
rtlink.py rtio: add support for latency compensation in phy 2016-12-14 19:16:07 +01:00