Sebastien Bourdeauducq 43e58c939c sayma: drop MasterDAC ... This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties. Now Sayma works fine with Kasli as a master, which is simpler.		2019-06-14 14:06:16 +08:00
..
amp	refactor targets	2018-01-22 18:25:10 +08:00
drtio	siphaser: improve ultrascale clock routing	2019-02-25 23:00:01 +08:00
dsp	sawg: don't use Cat() for signed signals	2018-06-09 07:33:47 +00:00
grabber	grabber: fix frame size off-by-1	2018-09-07 16:55:43 +02:00
rtio	suservo: add some more comments to the RTServoMem to clarify the RTIO interface (#1323)	2019-05-17 16:12:35 +01:00
serwb	serwb: support single-ended signals	2018-06-13 21:28:21 +08:00
suservo	suservo: add some more comments to the RTServoMem to clarify the RTIO interface (#1323)	2019-05-17 16:12:35 +01:00
targets	sayma: drop MasterDAC	2019-06-14 14:06:16 +08:00
test	Add gateware input event counter	2019-01-15 10:55:07 +00:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
eem.py	Add gateware input event counter	2019-01-15 10:55:07 +00:00
fmcdio_vhdci_eem.py	fmcdio_vhdci_eem: commit missing part of previous commit	2018-07-17 20:30:13 +08:00
jesd204_tools.py	jesd204sync: reset and check lock status of DDMTD helper PLL in firmware	2019-01-31 15:11:16 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
remote_csr.py	remote_csr: add sanity check of CSR CSV type column	2018-02-13 20:02:51 +08:00