artiq/artiq/gateware
Sebastien Bourdeauducq b8968262d7 Merge branch 'syncrtio' 2023-01-12 16:44:54 +08:00
..
amp gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
drtio test_write_underflow: decrease underflow delay 2023-01-11 12:02:51 +08:00
grabber grabber: fix frame size off-by-1 2018-09-07 16:55:43 +02:00
rtio rtio: remove support for async mode 2023-01-06 18:22:05 +08:00
suservo suservo: use default urukul profile 2022-01-10 16:21:39 +08:00
targets Merge branch 'syncrtio' 2023-01-12 16:44:54 +08:00
test test_write_underflow: decrease underflow delay 2023-01-11 12:02:51 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
eem.py differentiate phaser modes 2022-09-02 11:03:23 +00:00
eem_7series.py whitespace 2022-09-02 14:54:18 +00:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00