2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Commit Graph

1361 Commits

Author SHA1 Message Date
d6f47b3bb0 benchmarks/examples: give comm_serial a device
These examples/benchmarks require manual handholding in
many cases anyway. Also, for comm_tcp manual changes are required.

Instead of nursing a bunch of different pdb and ddbs,
we probably want to force the user to copy and edit a template
that we then gitignore.
2015-04-14 21:50:40 -06:00
a336c95d0a runtime/Makefile: work around echo vs bin/echo 2015-04-14 21:26:49 -06:00
f988ec318e pipistrello: fix csrs, make AMP default 2015-04-14 21:10:07 -06:00
9795e83bfc pdq2: continue work on coefficients 2015-04-14 18:18:49 -06:00
9e726d7dd1 ppro: ignore all async paths 2015-04-14 18:18:48 -06:00
70916aa0c5 pipistrello: tig _all_ async paths, add timing interference report 2015-04-14 18:18:48 -06:00
6a0e97f161 pdq2: refactor program_frame(), cleanup test, stall correctly
Once the Sequencer ack's a line, the Parser starts preparing the
next one. This includes jumping through the frame table if necessary.
To stall the Parser while the Sequencer executes the last line of a
frame and to ensure that the frame select lines can be set up and their
sampling is synchronized to a trigger, we add a triggered stall line
at the end of the frame.

When that line is triggered the Parser jumps through the table and starts
parsing the first line of the next frame. We let the duration of this
last stall line be 10 cycles (200ns@50MHz) to be able to distinguish this
sampling of the frame select lines from the triggering of the first line
in the next frame.

frame           f
parser     n     f 0
stb        __---________---___
trigger    ___----_______----_
ack        ____-__________-___
sequencer  n-1 n          0
2015-04-14 18:18:16 -06:00
bc1acef355 test/pdq2: don't write vcd 2015-04-14 18:18:16 -06:00
066adbdeac pipistrello: timing report 2015-04-14 18:18:16 -06:00
6217cf5392 pipistrello: basesoc, cleanup 2015-04-14 18:18:16 -06:00
4c10182c9f rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
c0f1708c20 targets/pipstrello: fix mem_map 2015-04-14 19:34:14 +08:00
ff9a7727d2 rtio: add rtlink definition (currently unused) 2015-04-13 22:19:18 +08:00
07b8e1292f artiq_flash: fix stderr redirections 2015-04-11 23:43:33 +08:00
8a2b8fc634 artiq_flash: do not always assume permission problems 2015-04-11 22:54:17 +08:00
Yann Sionneau
8a3be4eca0 artiq_flash: add support for kc705 2015-04-11 22:38:11 +08:00
a50f2c20ff targets/ppro: fix mem_map update 2015-04-11 21:59:29 +08:00
601f593ac4 targets/kc705: do not depend on particular Migen generated signal names 2015-04-11 21:46:57 +08:00
Florent Kermarrec
bdd02a064e targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :) 2015-04-11 21:32:46 +08:00
Florent Kermarrec
24b2bd7b6f soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds 2015-04-11 21:32:11 +08:00
fb75bd246e targets/kc705: make AMP the default 2015-04-11 17:16:25 +08:00
b492aad1c4 targets/kc705: enable Ethernet core 2015-04-10 13:15:32 +08:00
88e0aae16d coredevice: add comm_tcp 2015-04-10 01:22:03 +08:00
f427041ae9 coredevice/comm_serial: minor cleanup 2015-04-10 01:21:47 +08:00
cb2596bd81 coredevice/comm: split protocol to allow reuse for Ethernet 2015-04-10 00:59:35 +08:00
44304a33b2 soc,runtime: define RTIO FUD channel number in targets 2015-04-09 00:35:11 +08:00
efd1c24ed7 frontend: add artiq_compile tool to build default experiment 2015-04-07 15:41:32 +08:00
ca89b6d0ed worker_db: support read-only mode 2015-04-07 15:40:57 +08:00
fda4ee1a83 coredevice: add compile method 2015-04-07 15:40:25 +08:00
5e046dc5ce artiq_run: move parse_arguments and get_experiment to tools 2015-04-07 13:04:47 +08:00
2456e795dd conda: add missing entry_points 2015-04-07 11:17:47 +08:00
1ddcfc13fb conda: fix bitstream name 2015-04-07 11:17:25 +08:00
c8039e9dd2 doc: update Papilio Pro info 2015-04-07 00:09:08 +08:00
7e591bb1c7 targets: use _Peripherals/UP/AMP class names, share QC1 IO defs 2015-04-07 00:07:53 +08:00
1ed60e0829 gateware/amp: use new ModuleTransformer API 2015-04-06 23:54:53 +08:00
5538ad5c70 runtime: support RPC exceptions on AMP 2015-04-06 22:28:10 +08:00
45bb9d8840 runtime: support RPC and log on AMP 2015-04-06 19:40:12 +08:00
f26c53cb35 runtime: use KERNELCPU_PAYLOAD_ADDRESS on UP 2015-04-05 22:16:51 +08:00
0c62f0f69c runtime: remove generated service_table.h 2015-04-05 22:08:20 +08:00
72f9f7ed79 runtime: implement mailbox, use it for kernel startup, exceptions and termination 2015-04-05 22:07:34 +08:00
7ea9250b31 wavesynth: interpolate->coefficients 2015-04-05 04:43:27 -06:00
0bab73eece wavesynth/compute_samples: fix list mutation bug 2015-04-05 18:41:06 +08:00
9fd4594c53 interpolate: refactor discrete_compensate 2015-04-05 04:32:23 -06:00
75dfa95b4d wavesynth: move test code to unittests, fix mutability style 2015-04-05 04:24:44 -06:00
3257275782 worker_db: get_logger -> getLogger 2015-04-05 18:02:07 +08:00
1d5f467da7 pdq2: implement changes in trigger/jump semantics, add unittest
The unittests now runs the compute_samples.Synthesizer against the actual
gateware and verifies similarity (up to integer rounding errors).
2015-04-05 03:55:54 -06:00
e870b27830 wavesynth: new semantics, fix compensation
* "trigger" now means that the corresponding line will only start
  once the trigger line is high.
* "jump" is implicit as the last line in a frame must jump back.
* spline coefficients are now compensated for finite time step size
2015-04-05 03:55:54 -06:00
1f545346e3 wavesynth: implement silence, add defaults, fix bias 2015-04-05 03:55:54 -06:00
051b01f58e wavesynth: refactor testing code 2015-04-05 03:55:54 -06:00
1bca614d11 runtime: use UP/AMP terminology 2015-04-05 17:55:05 +08:00