17 Commits (35f30ddf054ba123c923efcd3a0ddf28c758ef36)

Author	SHA1	Message	Date
Spaqin	35f30ddf05	Expose TTLClockGen for Kasli JSONs (#1886)	2022-05-06 13:33:42 +08:00
Sebastien Bourdeauducq	37d0a5dc19	rtio/ttl: expose OE	2019-10-16 18:48:20 +08:00
David Nadlinger	a565f77538	Add gateware input event counter	2019-01-15 10:55:07 +00:00
Robert Jördens	e356150ac4	ttl_simple: support differential io	2018-03-06 14:27:19 +01:00
Sebastien Bourdeauducq	a7de58b604	rtio: Inout → InOut	2017-03-14 14:18:55 +08:00
Robert Jördens	f5f7acc1f8	ttl_simple: add pure Input ... (no Tristate for internal signals)	2016-10-10 17:13:23 +02:00
Sebastien Bourdeauducq	a7dd356d30	rtio/phy/ttl: support 'set sensitivity and sample' command (#218)	2016-09-07 15:42:09 +08:00
Sebastien Bourdeauducq	542a375305	rtio: remove NOP suppression capability ... Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows. The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows. This patch makes the behavior of RTIO more consistent and the code simpler.	2016-03-10 09:47:29 +08:00
Sebastien Bourdeauducq	e26147b2ac	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
Sebastien Bourdeauducq	58c0150822	ttl: improve clockgen doc	2015-07-05 19:07:13 +02:00
Sebastien Bourdeauducq	753d61b38f	complete support for TTL clock generator	2015-07-04 18:36:01 +02:00
Sebastien Bourdeauducq	2881d5f00a	gateware: add RTIO clock generator	2015-07-02 18:20:26 +02:00
Sebastien Bourdeauducq	b2af0f6cc3	soc,runtime: support TTL override	2015-06-09 19:51:02 +08:00
Sebastien Bourdeauducq	b81151eb42	soc: rtio monitor	2015-06-02 17:41:40 +08:00
Sebastien Bourdeauducq	cb65b1e322	rtio/phy/ttl_simple: reset sensitivity with RTIO logic	2015-05-02 16:17:31 +08:00
Sebastien Bourdeauducq	a61d701d47	rtio: decouple PHY reset from logic reset	2015-05-02 11:47:11 +08:00
Sebastien Bourdeauducq	4c10182c9f	rtio: refactor, use rtlink	2015-04-14 19:44:45 +08:00