77e6fdb7a7
artiq_flash: cleanup Sayma RTM management, support flashing AMC with RTM disconnected
2020-04-14 18:22:06 +08:00
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
e8b73876ab
comm_kernel: add Zynq runtime identifier
2020-04-12 17:25:14 +08:00
de57039e6e
comm_kernel: cleanup
2020-04-12 16:02:36 +08:00
9dc24f255e
comm_kernel: remove dead code
2020-04-12 15:06:46 +08:00
fb0ade77a9
firmware: fix non-DRTIO build
2020-04-10 17:23:17 +08:00
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
3c823a483a
sayma: improve DAC sync messaging (again)
2020-04-06 22:36:43 +08:00
4d601c2102
sayma: improve DAC sync messaging
2020-04-06 22:36:03 +08:00
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
facc0357d8
drtio: make sure receive buffer is drained after ping reply
2020-04-06 22:33:15 +08:00
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
8f608fa2fa
examples/sines_urukul_sayma: adapt for sayma v2, use 1 DAC only
2020-04-05 16:51:40 +08:00
Etienne Wodey
90d08988b2
language/environment: BooleanValue: fix type detection
...
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-04-04 15:37:04 +08:00
Etienne Wodey
9b03a365ed
language/environment: cast argument processor default values early
...
Fixes #1434 . Also add unit tests for some argument processors.
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-04-04 15:37:04 +08:00
371d923385
manual: nixpkgs 20.03
2020-04-04 13:05:46 +08:00
9294efabc0
manual: Kasli can get MAC address from EEPROM
2020-03-14 12:19:43 +08:00
4a8d361ace
soc: optimize programmable identifier
2020-03-12 23:09:13 +08:00
9e66dd7075
soc: reprogrammable identifier
2020-03-12 22:23:08 +08:00
380de177e7
rtio: fix wide output after RTIO refactoring
...
fixes 3d0c3cc1cf
2020-03-05 17:55:27 +00:00
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
8dbf30b23e
manual: mention integrated Kasli JTAG
2020-03-02 18:42:01 +08:00
8451e58fbe
ad9912: fix ftw width docstring
2020-02-27 02:11:12 +08:00
Paweł K
2a909839ff
artiq_flash: added option of specifying another username when connecting through SSH. ( #1429 )
...
Signed-off-by: Paweł Kulik <pawel.kulik@creotech.pl>
2020-02-19 19:44:11 +08:00
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
52ec849008
sayma: fix sysref_delay_dac
2020-02-05 19:04:01 +08:00
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
bf9f4e380a
si5324: program I2C mux on Metlino
2020-02-03 18:07:59 +08:00
ffb24e9fff
artiq_flash: use correct proxy bitstream for Metlino
2020-02-03 18:07:26 +08:00
5f8e20b1a1
artiq_sinara_tester: fix device_db filename
2020-01-31 10:26:58 +08:00
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
f4d8f77268
turn kasli_tester into a frontend tool
2020-01-21 16:13:04 +08:00
bfcbffcd8d
update smoltcp
...
This disables the 'log' features which does not compile, and may break net_trace. To be investigated later.
2020-01-21 13:58:23 +08:00
82cdb7f933
typo
2020-01-21 10:07:13 +08:00
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
c45a872cba
fastino: fix init, set_cfg
2020-01-20 13:25:00 +01:00
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
8f9948a1ff
kasli_sawgmaster: add basemod programming example
2020-01-20 20:14:24 +08:00
e427aaaa66
basemod_att: fix imports
2020-01-20 20:14:24 +08:00
62a52cb086
sayma: do not pollute the log with DAC status on success
2020-01-20 20:14:24 +08:00
6b428ef3be
sayma: initialize DAC before testing jesd::ready
2020-01-20 20:14:24 +08:00
7ab0282234
adf5355: style
2020-01-20 13:13:08 +01:00
9368c26d1c
mirny: add to manual
2020-01-20 13:13:08 +01:00
Etienne Wodey
da531404e8
artiq_ddb_template: add Mirny support
...
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
2020-01-20 13:13:08 +01:00
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
ec03767dcf
sayma: improve DAC status report
2020-01-20 18:22:06 +08:00
5c299de3b4
sayma: print DAC status on JESD not ready error
2020-01-20 18:21:29 +08:00
45efee724e
sayma: add JESD204 PHY done diagnostics
2020-01-20 12:47:31 +08:00
