mirror of https://github.com/m-labs/artiq.git
sayma: add JESD204 PHY done diagnostics
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@ -11,7 +11,12 @@ pub mod jesd {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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pub fn phy_done(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_phy_done_read)() != 0
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}
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}
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pub fn ready(dacno: u8) -> bool {
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@ -84,7 +89,11 @@ pub mod jdac {
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info!("DAC-{} initializing...", dacno);
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jesd::enable(dacno, true);
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clock::spin_us(10);
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clock::spin_us(10_000);
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if !jesd::phy_done(dacno) {
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error!("JESD core PHY not done");
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return Err("JESD core PHY not done");
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}
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if !jesd::ready(dacno) {
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error!("JESD core reported not ready");
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return Err("JESD core reported not ready");
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