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examples/sines_urukul_sayma: adapt for sayma v2, use 1 DAC only
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@ -25,50 +25,42 @@ device_db = {
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},
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}
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for i in range(8):
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device_db["ttl" + str(i)] = {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut" if i < 4 else "TTLOut",
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"arguments": {"channel": 1+i},
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}
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device_db.update(
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spi_urukul0={
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 9}
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"arguments": {"channel": 0}
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},
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ttl_urukul0_io_update={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 10}
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"arguments": {"channel": 1}
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},
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ttl_urukul0_sw0={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 11}
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"arguments": {"channel": 2}
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},
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ttl_urukul0_sw1={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 12}
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"arguments": {"channel": 3}
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},
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ttl_urukul0_sw2={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 13}
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"arguments": {"channel": 4}
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},
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ttl_urukul0_sw3={
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 14}
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"arguments": {"channel": 5}
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},
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urukul0_cpld={
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"type": "local",
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@ -8,9 +8,6 @@ class SinesUrukulSayma(EnvExperiment):
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# Urukul clock output syntonized to the RTIO clock.
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# Can be used as HMC830 reference on Sayma RTM.
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# The clock output on Sayma AMC cannot be used, as it is derived from
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# another Si5324 output than the GTH, and the two Si5324 output dividers
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# are not synchronized with each other.
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# When using this reference, Sayma must be recalibrated every time Urukul
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# is rebooted, as Urukul is not synchronized to the Kasli.
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self.urukul_hmc_ref = self.get_device("urukul0_ch3")
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@ -19,8 +16,16 @@ class SinesUrukulSayma(EnvExperiment):
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# When testing sync, do not reboot Urukul, as it is not
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# synchronized to the Kasli.
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self.urukul_meas = [self.get_device("urukul0_ch" + str(i)) for i in range(3)]
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
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# The same waveform is output on all first 4 SAWG channels (first DAC).
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(4)]
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self.basemod = self.get_device("basemod_att0")
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self.rfsws = [self.get_device("sawg_sw"+str(i)) for i in range(4)]
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# DRTIO destinations:
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# 0: local
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# 1: Sayma AMC
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# 2: Sayma RTM
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@kernel
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def drtio_is_up(self):
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for i in range(3):
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@ -61,6 +66,15 @@ class SinesUrukulSayma(EnvExperiment):
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self.core.reset()
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delay(10*ms)
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self.basemod.reset()
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delay(10*ms)
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self.basemod.set(3.0, 3.0, 3.0, 3.0)
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delay(10*ms)
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for rfsw in self.rfsws:
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delay(1*ms)
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rfsw.on()
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for sawg in self.sawgs:
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delay(1*ms)
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sawg.reset()
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