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029e0d95b7
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drtio: simple fixes
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2016-10-24 23:10:15 +08:00 |
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c39987b617
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drtio: handle underflow/sequence error CSRs
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2016-10-24 20:46:55 +08:00 |
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7dd6eb2f5e
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drtio: add RT write controller
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2016-10-24 19:50:13 +08:00 |
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83bec06226
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drtio: fifo level -> fifo space
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2016-10-24 15:59:12 +08:00 |
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|
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aa8e211735
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drtio/rt_packets: fix
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2016-10-22 13:03:35 +08:00 |
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|
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449d1c4dc6
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rtio: export CDC modules
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2016-10-22 13:03:10 +08:00 |
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|
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67c19ab178
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drtio: RTPacketMaster RX, untested
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2016-10-22 01:04:14 +08:00 |
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|
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3b4a40401a
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drtio: RTPacketMaster TX (WIP)
|
2016-10-21 22:46:14 +08:00 |
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|
|
1e313afe64
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drtio: CrossDomainNotification
|
2016-10-21 22:45:45 +08:00 |
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|
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c71c4c89e0
|
drtio: change data direction in _CrossDomainRequest
|
2016-10-21 22:44:47 +08:00 |
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whitequark
|
6872017449
|
gateware: extend mailbox to 3 entries.
|
2016-10-21 12:09:14 +00:00 |
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|
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6a88229e6a
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drtio: CrossDomainRequest
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2016-10-20 23:37:59 +08:00 |
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|
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062aca2a6b
|
conda/phaser: build-depend on jesd204b
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2016-10-19 14:44:54 +02:00 |
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|
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6aa13fbf25
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master/worker_db: set default value for archive
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2016-10-19 20:12:16 +08:00 |
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|
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9790c5d9ed
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drtio/iot: FIFO level
|
2016-10-19 18:04:03 +08:00 |
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|
|
bf942fc228
|
ksupport: adapt to dyld_load()
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2016-10-18 11:37:27 +02:00 |
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|
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71480c4d15
|
drtio: fix mmcm_mult
|
2016-10-18 17:28:03 +08:00 |
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|
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5d184f8061
|
master: keep dataset manager consistent when set_dataset is called with contradictory attributes
|
2016-10-18 17:11:07 +08:00 |
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|
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69d96b0158
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master: archive input datasets. Closes #587
|
2016-10-18 17:11:07 +08:00 |
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ed2624545f
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master: ensure same dataset is in broadcast and local when mutating
|
2016-10-18 17:11:07 +08:00 |
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|
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1908339d4e
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scheduler: default submission arguments, closes #577
|
2016-10-18 17:11:06 +08:00 |
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|
|
54f05b6fc1
|
ksupport: kernel_run lookup with dyld (closes #590)
adapt to misoc change
|
2016-10-18 10:07:07 +02:00 |
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|
|
78700a67bc
|
sawg: fast-math
|
2016-10-18 10:05:51 +02:00 |
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|
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b2327cf808
|
sawg: core is kernel_invariant
|
2016-10-18 10:05:51 +02:00 |
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0e41725e2d
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pdq2: sync with pdq2
|
2016-10-18 09:43:46 +02:00 |
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|
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69099691f7
|
doc: clarify usage of pause/check_pause, closes #571
|
2016-10-17 20:08:15 +08:00 |
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|
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02adccf4a2
|
dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572
|
2016-10-17 19:57:59 +08:00 |
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|
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e7dbed3b02
|
gateware: KC705 satellite target
|
2016-10-17 19:23:45 +08:00 |
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|
|
9752ffe3d1
|
drtio: various fixes
|
2016-10-17 19:23:08 +08:00 |
|
|
|
cce29e8b83
|
gateware/spi: fix import
|
2016-10-17 14:47:19 +08:00 |
|
|
|
b6002529cf
|
gateware/spi: fix import
|
2016-10-17 14:07:11 +08:00 |
|
|
|
85834976d9
|
gateware/spi: fix import
|
2016-10-17 14:06:35 +08:00 |
|
whitequark
|
6da1f39670
|
runtime: fix use of $(realpath) in Makefile.
|
2016-10-17 00:11:02 +00:00 |
|
whitequark
|
f10a4498c7
|
test: fix printf specifier.
|
2016-10-16 23:54:29 +00:00 |
|
whitequark
|
2a9e370840
|
llvm_ir_generator: make sure RPC allocations are not underaligned.
|
2016-10-16 16:43:03 +00:00 |
|
whitequark
|
7618907cad
|
runtime: use i64 for watchdog timeout, not i32.
|
2016-10-16 16:32:43 +00:00 |
|
whitequark
|
a8c017bfcc
|
runtime: port ksupport to Rust.
|
2016-10-16 16:32:43 +00:00 |
|
whitequark
|
fee75bd50f
|
runtime: remove some redundant libm functions copied inline.
|
2016-10-16 16:25:29 +00:00 |
|
|
|
6a683c712b
|
phaser: work around for unreliable transciever init
|
2016-10-16 16:01:23 +02:00 |
|
|
|
d3b274fc4d
|
drtio: synchronizer MMCM
|
2016-10-16 17:40:58 +08:00 |
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|
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03d3a85e75
|
drtio: RX clock alignment and ready
|
2016-10-15 18:36:27 +08:00 |
|
Florent Kermarrec
|
0259c80015
|
phaser/kc705: remove transceiver initialization workaround
|
2016-10-14 19:06:43 +02:00 |
|
|
|
9ba6be8796
|
phaser: speed up ad9154_test_status
|
2016-10-14 13:23:14 +02:00 |
|
|
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4968de053c
|
phaser: update README
|
2016-10-14 13:21:54 +02:00 |
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|
|
4b4fd32e3d
|
phaser: add another sawg demo
|
2016-10-14 13:21:42 +02:00 |
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d16068dd9b
|
sawg: absolute phase updates
|
2016-10-14 12:42:08 +02:00 |
|
|
|
9b43f09c1d
|
phaser: cleanup prbs
|
2016-10-14 11:56:10 +02:00 |
|
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|
b41b9de905
|
phaser: tag jesd as clock net
|
2016-10-14 10:46:33 +02:00 |
|
|
|
4ea3dea217
|
phaser: broad spectrum antibiotics with xilinx false paths
|
2016-10-14 10:22:03 +02:00 |
|
|
|
e400f8d672
|
phaser: add two more registers before jesd
|
2016-10-14 09:54:56 +02:00 |
|
