This turned out to be a race between the dashboard's dataset db
subscriber being initialised and the applet "embed" request, with
artiq.applet.simple not being able to handle the unexpected "mod"
message. We were only handling the other ordering outcome of this
race before.
This maps basic Python types (float, str, bool, np.int32, np.int64) as well as
some generics (list, tuple) to ARTIQ's own type instances.
Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>
The type checker/inferer visits every node in an AST tree, including
function return annotations. This means for a function definition like
def f() -> TTuple([TInt32, TBool]):
...
We attempt to type check the list [TInt32, TBool], which generates the
unification constraint builtins.TBool ~ builtins.TInt. This causes an
internal error due to compiler weirdness.
We can avoid this by just nulling-out the return annotation in the
embedding stage. The return type isn't actually used anywhere (it's
extracted via the inspect module instead), so this is entirely safe.
Arguments aren't affected by this, as we already nulled out the
annotation (see visit_arg in embedding.py).
Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>
The original fix in 21574bdfa9
was incomplete, as it only addressed the TInstance types, but
not their linked (typ.constructor) TConstructor instances.
This would (potentially among other issues) cause assertion
errors in llvm_ir_generator due to the wrong associated globals
being referenced; see added test case for an example that
previously caused such a crash.
Also modified the name collision detection from O(len(type_map))
(so quadratic overall in the number of custom types) to cache
names in sets for O(1) lookup.
* ddb: generate shuttler coredevice entries
* ddb: split-off all DRTIO-over-EEM peripherals
Only EFC uses DRTIO-over-EEM at this moment. It will be relevant to phaser-DRTIO in the future.
* ddb: generalize efc processing into drtio-over-eem peripherals
* ddb: check DRTIO role validity before processing
This example code:
- Demonstrates the init flow for Shuttler
- Blinks LED L0, L1
- Demonstrates the real-time control of relay
- Includes example fns for configuring the PDQ Output Channel in mu
- Intend to maintain the same pipeline latency across all DACs on Shuttler
- Force the RETIMER-CLK to be PHASE 1 on all DACs
- See Issue #2200 for details
