M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

shuttler: cleanup

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2023-10-06 14:55:51 +08:00
parent e63e2a2897
commit 0131a8bef2
4 changed files with 19 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
artiq/coredevice/shuttler.py
View File

@ -1,5 +1,3 @@
import numpy
from artiq.language.core import *
from artiq.language.types import *
from artiq.coredevice.rtio import rtio_output, rtio_input_data
@ -106,7 +104,7 @@ class Config:
return rtio_input_data(self.channel)
class Volt:
class DCBias:
"""Shuttler Core cubic DC-bias spline.
A Shuttler channel can generate a waveform `w(t)` that is the sum of a
@ -138,7 +136,7 @@ class Volt:
def set_waveform(self, a0: TInt32, a1: TInt32, a2: TInt64, a3: TInt64):
"""Set the DC-bias spline waveform.
Given `a(t)` as defined in :class:`Volt`, the coefficients should be
Given `a(t)` as defined in :class:`DCBias`, the coefficients should be
configured by the following formulae.
.. math::
@ -181,7 +179,7 @@ class Volt:
delay_mu(int64(self.core.ref_multiplier))
class Dds:
class DDS:
"""Shuttler Core DDS spline.
A Shuttler channel can generate a waveform `w(t)` that is the sum of a
@ -218,7 +216,7 @@ class Dds:
c0: TInt32, c1: TInt32, c2: TInt32):
"""Set the DDS spline waveform.
Given `b(t)` and `c(t)` as defined in :class:`Dds`, the coefficients
Given `b(t)` and `c(t)` as defined in :class:`DDS`, the coefficients
should be configured by the following formulae.
.. math::
@ -295,7 +293,7 @@ class Trigger:
Each bit corresponds to a Shuttler waveform generator core. Setting
`trig_out` bits commits the pending coefficient update (from
`set_waveform` in :class:`Volt` and :class:`Dds`) to the Shuttler Core
`set_waveform` in :class:`DCBias` and :class:`DDS`) to the Shuttler Core
synchronously.
:param trig_out: Coefficient update trigger bits. The MSB corresponds
@ -582,7 +580,7 @@ class ADC:
:meth:`Config.set_offset`
:param volts: A list of all 16 cubic DC-bias spline.
(See :class:`Volt`)
(See :class:`DCBias`)
:param trigger: The Shuttler spline coefficient update trigger.
:param config: The Shuttler Core configuration registers.
:param samples: A list of sample voltages for calibration. There must

6
artiq/examples/kasli_shuttler/kasli_efc.json → artiq/examples/kasli_shuttler/kasli_shuttler.json
View File

@ -1,12 +1,12 @@
{
"target": "kasli",
"variant": "master",
"variant": "shuttlerdemo",
"hw_rev": "v2.0",
"base": "master",
"drtio_role": "master",
"peripherals": [
{
"type": "shuttler",
"ports": [0]
"ports": [0]
},
{
"type": "dio",

14
artiq/examples/kasli_shuttler/repository/shuttler.py
View File

@ -60,7 +60,7 @@ class Shuttler(EnvExperiment):
self.shuttler0_leds = [ self.get_device("shuttler0_led{}".format(i)) for i in range(2) ]
self.setattr_device("shuttler0_config")
self.setattr_device("shuttler0_trigger")
self.shuttler0_volt = [ self.get_device("shuttler0_volt{}".format(i)) for i in range(16) ]
self.shuttler0_dcbias = [ self.get_device("shuttler0_dcbias{}".format(i)) for i in range(16) ]
self.shuttler0_dds = [ self.get_device("shuttler0_dds{}".format(i)) for i in range(16) ]
self.setattr_device("shuttler0_relay")
self.setattr_device("shuttler0_adc")
@ -102,7 +102,7 @@ class Shuttler(EnvExperiment):
@kernel
def shuttler_channel_reset(self, ch):
self.shuttler0_volt[ch].set_waveform(
self.shuttler0_dcbias[ch].set_waveform(
a0=0,
a1=0,
a2=0,
@ -226,7 +226,7 @@ class Shuttler(EnvExperiment):
delay(500*us)
## Step 5 ##
self.shuttler0_volt[0].set_waveform(
self.shuttler0_dcbias[0].set_waveform(
a0=shuttler_volt_amp_mu(-5.0),
a1=int32(shuttler_volt_damp_mu(0.01)),
a2=0,
@ -241,7 +241,7 @@ class Shuttler(EnvExperiment):
c1=shuttler_freq_mu(end_f_MHz),
c2=0,
)
self.shuttler0_volt[1].set_waveform(
self.shuttler0_dcbias[1].set_waveform(
a0=shuttler_volt_amp_mu(-5.0),
a1=int32(shuttler_volt_damp_mu(0.01)),
a2=0,
@ -260,7 +260,7 @@ class Shuttler(EnvExperiment):
delay(1000*us)
## Step 6 ##
self.shuttler0_volt[0].set_waveform(
self.shuttler0_dcbias[0].set_waveform(
a0=shuttler_volt_amp_mu(-2.5),
a1=int32(shuttler_volt_damp_mu(0.01)),
a2=0,
@ -280,7 +280,7 @@ class Shuttler(EnvExperiment):
delay(500*us)
## Step 7 ##
self.shuttler0_volt[0].set_waveform(
self.shuttler0_dcbias[0].set_waveform(
a0=shuttler_volt_amp_mu(2.5),
a1=int32(shuttler_volt_damp_mu(-0.01)),
a2=0,
@ -327,4 +327,4 @@ class Shuttler(EnvExperiment):
# The actual output voltage is limited by the hardware, the calculated calibration gain and offset.
# For example, if the system has a calibration gain of 1.06, then the max output voltage = 10 / 1.06 = 9.43V.
# Setting a value larger than 9.43V will result in overflow.
self.shuttler0_adc.calibrate(self.shuttler0_volt, self.shuttler0_trigger, self.shuttler0_config)
self.shuttler0_adc.calibrate(self.shuttler0_dcbias, self.shuttler0_trigger, self.shuttler0_config)

6
artiq/frontend/artiq_ddb_template.py
View File

@ -652,10 +652,10 @@ class PeripheralManager:
channel=rtio_offset + next(channel))
for i in range(16):
self.gen("""
device_db["{name}_volt{ch}"] = {{
device_db["{name}_dcbias{ch}"] = {{
"type": "local",
"module": "artiq.coredevice.shuttler",
"class": "Volt",
"class": "DCBias",
"arguments": {{"channel": 0x{channel:06x}}},
}}""",
name=shuttler_name,
@ -665,7 +665,7 @@ class PeripheralManager:
device_db["{name}_dds{ch}"] = {{
"type": "local",
"module": "artiq.coredevice.shuttler",
"class": "Dds",
"class": "DDS",
"arguments": {{"channel": 0x{channel:06x}}},
}}""",
name=shuttler_name,