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Simplify OOB reset by clock division (#2217)
* oob: simply logic by dividing into clk100 * replace clk100 clk ctrl with clk200 async reset * fix comment (singular/plural) * oob reset: invoke platform commands locally * cleanup * oob reset: add async reset import * fix duplicated comment
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@ -1,4 +1,5 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from misoc.cores.code_8b10b import SingleEncoder, Decoder
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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@ -396,53 +397,78 @@ class SerdesSingle(Module):
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class OOBReset(Module):
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def __init__(self, iserdes_o):
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ce_counter = Signal(13)
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activity_ce = Signal()
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transition_ce = Signal()
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def __init__(self, platform, iserdes_o):
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self.clock_domains.cd_clk100 = ClockDomain()
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self.specials += [
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Instance("BUFR",
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i_I=ClockSignal("clk200"),
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o_O=ClockSignal("clk100"),
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p_BUFR_DIVIDE="2"),
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AsyncResetSynchronizer(self.cd_clk100, ResetSignal("clk200")),
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]
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self.sync.clk200 += Cat(ce_counter, activity_ce).eq(ce_counter + 1)
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self.comb += transition_ce.eq(ce_counter[0])
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idle_low_meta = Signal()
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idle_high_meta = Signal()
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idle_low = Signal()
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idle_high = Signal()
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idle = Signal()
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self.rst = Signal(reset=1)
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# Detect the lack of transitions (idle) within 2 clk200 cycles
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self.specials += [
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Instance("FDCE", p_INIT=1, i_D=1, i_CLR=iserdes_o,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_low_meta,
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attr={"async_reg", "ars_ff1"}),
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Instance("FDCE", p_INIT=1, i_D=idle_low_meta, i_CLR=0,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_low,
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attr={"async_reg", "ars_ff2"}),
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# Detect the lack of transitions (idle) within a clk100 cycle
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for idle, source in [
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(idle_low, iserdes_o), (idle_high, ~iserdes_o)]:
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idle_meta = Signal()
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ff_pair = [ff1, ff2] = [
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Instance("FDCE", p_INIT=1, i_D=1, i_CLR=source,
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i_CE=1, i_C=ClockSignal("clk100"), o_Q=idle_meta,
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attr={"async_reg"}),
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Instance("FDCE", p_INIT=1, i_D=idle_meta, i_CLR=0,
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i_CE=1, i_C=ClockSignal("clk100"), o_Q=idle,
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attr={"async_reg"}),
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]
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self.specials += ff_pair
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Instance("FDCE", p_INIT=1, i_D=1, i_CLR=~iserdes_o,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_high_meta,
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attr={"async_reg", "ars_ff1"}),
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Instance("FDCE", p_INIT=1, i_D=idle_high_meta, i_CLR=0,
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i_CE=transition_ce, i_C=ClockSignal("clk200"), o_Q=idle_high,
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attr={"async_reg", "ars_ff2"}),
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]
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platform.add_platform_command(
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"set_false_path -quiet -to {ff1}/CLR", ff1=ff1)
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# Capture transition detected by FF1/Q in FF2/D
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platform.add_platform_command(
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"set_max_delay 2 -quiet "
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"-from {ff1}/Q -to {ff2}/D", ff1=ff1, ff2=ff2)
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# Detect activity for the last 2**13 clk200 cycles
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# The 2**13 cycles are fully partitioned into 2**12 time segments of 2
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# cycles in duration. If there exists 2-cycle time segment without
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# signal level transition, rst is asserted.
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self.sync.clk200 += [
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If(activity_ce,
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idle.eq(0),
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self.rst.eq(idle),
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),
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# Detect activity for the last 2**15 clk100 cycles
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self.submodules.fsm = fsm = ClockDomainsRenamer("clk100")(
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FSM(reset_state="WAIT_TRANSITION"))
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counter = Signal(15, reset=0x7FFF)
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# Keep sysclk reset asserted until transition is detected for a
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# continuous 2**15 clk100 cycles
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fsm.act("WAIT_TRANSITION",
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self.rst.eq(1),
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If(idle_low | idle_high,
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idle.eq(1),
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self.rst.eq(1),
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),
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]
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NextValue(counter, 0x7FFF),
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).Else(
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If(counter == 0,
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NextState("WAIT_NO_TRANSITION"),
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NextValue(counter, 0x7FFF),
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).Else(
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NextValue(counter, counter - 1),
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)
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)
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)
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# Reassert sysclk reset if there are no transition for the last 2**15
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# clk100 cycles.
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fsm.act("WAIT_NO_TRANSITION",
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self.rst.eq(0),
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If(idle_low | idle_high,
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If(counter == 0,
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NextState("WAIT_TRANSITION"),
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NextValue(counter, 0x7FFF),
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).Else(
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NextValue(counter, counter - 1),
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)
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).Else(
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NextValue(counter, 0x7FFF),
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)
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)
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class EEMSerdes(Module, TransceiverInterface, AutoCSR):
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@ -526,7 +552,7 @@ class EEMSerdes(Module, TransceiverInterface, AutoCSR):
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self.submodules += serdes_list
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self.submodules.oob_reset = OOBReset(serdes_list[0].rx_serdes.o[0])
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self.submodules.oob_reset = OOBReset(platform, serdes_list[0].rx_serdes.o[0])
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self.rst = self.oob_reset.rst
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self.rst.attr.add("no_retiming")
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