artiq/artiq/firmware/runtime/main.rs

254 lines
7.3 KiB
Rust
Raw Normal View History

2016-08-17 16:39:05 +08:00
#![no_std]
#![feature(alloc, lang_items, global_allocator, repr_align, attr_literals)]
2016-08-17 16:39:05 +08:00
2017-04-19 17:38:24 +08:00
extern crate alloc;
extern crate cslice;
2016-09-29 02:25:25 +08:00
#[macro_use]
extern crate log;
extern crate byteorder;
extern crate fringe;
extern crate smoltcp;
extern crate alloc_list;
#[macro_use]
extern crate std_artiq as std;
extern crate logger_artiq;
extern crate backtrace_artiq;
#[macro_use]
2016-12-31 21:32:50 +08:00
extern crate board;
extern crate board_artiq;
extern crate proto;
extern crate amp;
#[cfg(has_drtio)]
extern crate drtioaux;
2016-08-17 16:39:05 +08:00
2017-10-25 10:31:27 +08:00
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
use board::config;
2017-12-28 22:40:15 +08:00
#[cfg(has_ethmac)]
use board::ethmac;
use proto::{mgmt_proto, analyzer_proto, moninj_proto, rpc_proto, session_proto, kernel_proto};
use amp::{mailbox, rpc_queue};
2016-08-30 19:20:04 +08:00
#[cfg(has_rtio_core)]
2016-12-09 19:24:00 +08:00
mod rtio_mgt;
2016-09-30 04:56:35 +08:00
mod urc;
mod sched;
2016-10-02 02:24:53 +08:00
mod cache;
mod rtio_dma;
mod mgmt;
mod kernel;
mod kern_hwreq;
mod watchdog;
2016-09-30 04:56:35 +08:00
mod session;
#[cfg(any(has_rtio_moninj, has_drtio))]
2016-10-04 20:38:52 +08:00
mod moninj;
2016-10-05 13:59:38 +08:00
#[cfg(has_rtio_analyzer)]
mod analyzer;
fn startup() {
board::clock::init();
info!("ARTIQ runtime starting...");
info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
info!("gateware version {}", board::ident::read(&mut [0; 64]));
#[cfg(has_serwb_phy_amc)]
board_artiq::serwb::wait_init();
let t = board::clock::get_ms();
info!("press 'e' to erase startup and idle kernels...");
while board::clock::get_ms() < t + 1000 {
if unsafe { board::csr::uart::rxtx_read() == b'e' } {
config::remove("startup_kernel").unwrap();
config::remove("idle_kernel").unwrap();
info!("startup and idle kernels erased");
break
}
}
info!("continuing boot");
#[cfg(has_i2c)]
board_artiq::i2c::init();
2017-12-21 23:08:56 +08:00
#[cfg(si5324_free_running)]
setup_si5324_free_running();
#[cfg(has_hmc830_7043)]
board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
#[cfg(has_ad9154)]
board_artiq::ad9154::init().expect("cannot initialize AD9154");
#[cfg(has_ethmac)]
startup_ethernet();
#[cfg(not(has_ethmac))]
{
info!("done");
loop {}
}
}
2017-12-21 23:08:56 +08:00
#[cfg(si5324_free_running)]
fn setup_si5324_free_running()
{
// 150MHz output (hardcoded)
2017-12-28 15:45:45 +08:00
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings {
2017-12-21 23:08:56 +08:00
n1_hs : 9,
nc1_ls : 4,
n2_hs : 10,
n2_ls : 33732,
n31 : 9370,
n32 : 7139,
bwsel : 3
};
2017-12-28 15:45:45 +08:00
board_artiq::si5324::setup(&SI5324_SETTINGS).expect("cannot initialize Si5324");
2017-12-21 23:08:56 +08:00
}
#[cfg(has_ethmac)]
fn startup_ethernet() {
let hardware_addr;
match config::read_str("mac", |r| r.map(|s| s.parse())) {
Ok(Ok(addr)) => {
hardware_addr = addr;
info!("using MAC address {}", hardware_addr);
}
_ => {
hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x01]);
warn!("using default MAC address {}; consider changing it", hardware_addr);
}
}
let protocol_addr;
match config::read_str("ip", |r| r.map(|s| s.parse())) {
Ok(Ok(addr)) => {
protocol_addr = addr;
info!("using IP address {}", protocol_addr);
}
_ => {
protocol_addr = IpAddress::v4(192, 168, 1, 50);
info!("using default IP address {}", protocol_addr);
}
}
2017-08-30 22:35:45 +08:00
// fn _net_trace_writer<U>(timestamp: u64, printer: smoltcp::wire::PrettyPrinter<U>)
// where U: smoltcp::wire::pretty_print::PrettyPrint {
// let seconds = timestamp / 1000;
// let micros = timestamp % 1000 * 1000;
2017-12-26 22:33:56 +08:00
// print!("\x1b[37m[{:6}.{:06}s]\n{}\x1b[0m\n", seconds, micros, printer)
2017-08-30 22:35:45 +08:00
// }
2017-11-22 16:09:06 +08:00
let net_device = unsafe { ethmac::EthernetDevice::new() };
2017-08-30 22:35:45 +08:00
// let net_device = smoltcp::phy::EthernetTracer::new(net_device, _net_trace_writer);
2017-11-22 16:09:06 +08:00
let mut neighbor_cache_storage = [None; 8];
2017-12-19 23:51:03 +08:00
let neighbor_cache =
smoltcp::iface::NeighborCache::new(&mut neighbor_cache_storage[..]);
let mut interface =
smoltcp::iface::EthernetInterfaceBuilder::new(net_device)
.neighbor_cache(neighbor_cache)
.ethernet_addr(hardware_addr)
.ip_addrs([IpCidr::new(protocol_addr, 0)])
.finalize();
let mut scheduler = sched::Scheduler::new();
let io = scheduler.io();
#[cfg(has_rtio_core)]
rtio_mgt::startup(&io);
io.spawn(4096, mgmt::thread);
io.spawn(16384, session::thread);
#[cfg(any(has_rtio_moninj, has_drtio))]
io.spawn(4096, moninj::thread);
#[cfg(has_rtio_analyzer)]
io.spawn(4096, analyzer::thread);
match config::read_str("log_level", |r| r.map(|s| s.parse())) {
Ok(Ok(log_level_filter)) => {
info!("log level set to {} by `log_level` config key",
log_level_filter);
2018-01-01 19:45:55 +08:00
log::set_max_level(log_level_filter);
}
_ => info!("log level set to INFO by default")
}
match config::read_str("uart_log_level", |r| r.map(|s| s.parse())) {
Ok(Ok(uart_log_level_filter)) => {
info!("UART log level set to {} by `uart_log_level` config key",
uart_log_level_filter);
logger_artiq::BufferLogger::with(|logger|
logger.set_uart_log_level(uart_log_level_filter));
}
_ => info!("UART log level set to INFO by default")
}
let mut net_stats = ethmac::EthernetStatistics::new();
loop {
scheduler.run();
2017-12-26 22:33:56 +08:00
{
let sockets = &mut *scheduler.sockets().borrow_mut();
2017-12-26 22:33:56 +08:00
loop {
match interface.poll(sockets, board::clock::get_ms()) {
Ok(true) => (),
Ok(false) => break,
Err(smoltcp::Error::Unrecognized) => (),
Err(err) => warn!("network error: {}", err)
}
}
}
2017-12-15 14:07:16 +08:00
if let Some(_net_stats_diff) = net_stats.update() {
warn!("ethernet mac:{}", ethmac::EthernetStatistics::new());
}
}
}
#[global_allocator]
static mut ALLOC: alloc_list::ListAlloc = alloc_list::EMPTY;
static mut LOG_BUFFER: [u8; 1<<17] = [0; 1<<17];
#[no_mangle]
pub extern fn main() -> i32 {
unsafe {
extern {
static mut _fheap: u8;
static mut _eheap: u8;
}
ALLOC.add_range(&mut _fheap, &mut _eheap);
2017-04-19 17:38:24 +08:00
logger_artiq::BufferLogger::new(&mut LOG_BUFFER[..]).register(startup);
0
}
}
2016-08-17 16:39:05 +08:00
#[no_mangle]
pub extern fn exception(vect: u32, _regs: *const u32, pc: u32, ea: u32) {
panic!("exception {:?} at PC 0x{:x}, EA 0x{:x}", vect, pc, ea)
2016-08-17 16:39:05 +08:00
}
2016-10-07 14:27:10 +08:00
#[no_mangle]
pub extern fn abort() {
println!("aborted");
loop {}
2016-10-07 14:27:10 +08:00
}
#[no_mangle]
#[lang = "panic_fmt"]
pub extern fn panic_fmt(args: core::fmt::Arguments, file: &'static str, line: u32) -> ! {
println!("panic at {}:{}: {}", file, line, args);
println!("backtrace for software version {}:",
include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
let _ = backtrace_artiq::backtrace(|ip| {
println!("{:#08x}", ip);
});
if config::read_str("panic_reset", |r| r == Ok("1")) {
println!("restarting...");
unsafe { board::boot::reset() }
} else {
println!("halting.");
println!("use `artiq_coreconfig write -s panic_reset 1` to restart instead");
loop {}
}
}