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firmware: fix sayma_amc_standalone build with sawg.

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This commit is contained in:
whitequark 2017-12-28 08:15:51 +00:00
parent 4ea801b2ea
commit 8f33061a6d
5 changed files with 63 additions and 64 deletions
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3
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -1,5 +1,4 @@
use csr;
use clock;
use board::{csr, clock};
use ad9154_reg;
fn spi_setup(dacno: u8) {

7
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -11,7 +11,7 @@
*/
mod clock_mux {
use csr;
use board::csr;
const CLK_SRC_EXT_SEL : u8 = 1 << 0;
const REF_CLK_SRC_SEL : u8 = 1 << 1;
@ -28,8 +28,7 @@ mod clock_mux {
}
mod hmc830 {
use clock;
use csr;
use board::{csr, clock};
const HMC830_WRITES: [(u8, u32); 16] = [
(0x0, 0x20),
@ -117,7 +116,7 @@ mod hmc830 {
}
mod hmc7043 {
use csr;
use board::csr;
include!(concat!(env!("OUT_DIR"), "/hmc7043_writes.rs"));

2
artiq/firmware/libboard_artiq/serwb.rs
View File

@ -1,4 +1,4 @@
use csr;
use board::csr;
pub fn wait_init() {
info!("waiting for AMC/RTM serwb bridge to be ready...");

109
artiq/firmware/libboard_artiq/spi.rs
View File

@ -1,66 +1,67 @@
#[cfg(has_converter_spi)]
use csr;
mod imp {
use board::csr;
#[cfg(has_converter_spi)]
pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
if busno != 0 {
return Err(())
pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
if busno != 0 {
return Err(())
}
unsafe {
csr::converter_spi::offline_write(1);
csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
csr::converter_spi::clk_phase_write(flags >> 5 & 1);
csr::converter_spi::lsb_first_write(flags >> 6 & 1);
csr::converter_spi::half_duplex_write(flags >> 7 & 1);
csr::converter_spi::clk_div_write_write(write_div);
csr::converter_spi::clk_div_read_write(read_div);
csr::converter_spi::offline_write(0);
}
Ok(())
}
unsafe {
csr::converter_spi::offline_write(1);
csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
csr::converter_spi::clk_phase_write(flags >> 5 & 1);
csr::converter_spi::lsb_first_write(flags >> 6 & 1);
csr::converter_spi::half_duplex_write(flags >> 7 & 1);
csr::converter_spi::clk_div_write_write(write_div);
csr::converter_spi::clk_div_read_write(read_div);
csr::converter_spi::offline_write(0);
}
Ok(())
}
#[cfg(has_converter_spi)]
pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8) -> Result<(), ()> {
if busno != 0 {
return Err(())
pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8)
-> Result<(), ()> {
if busno != 0 {
return Err(())
}
unsafe {
csr::converter_spi::cs_write(chip_select as _);
csr::converter_spi::xfer_len_write_write(write_length);
csr::converter_spi::xfer_len_read_write(read_length);
}
Ok(())
}
unsafe {
csr::converter_spi::cs_write(chip_select as _);
csr::converter_spi::xfer_len_write_write(write_length);
csr::converter_spi::xfer_len_read_write(read_length);
}
Ok(())
}
#[cfg(has_converter_spi)]
pub fn write(busno: u8, data: u32) -> Result<(), ()> {
if busno != 0 {
return Err(())
pub fn write(busno: u8, data: u32) -> Result<(), ()> {
if busno != 0 {
return Err(())
}
unsafe {
csr::converter_spi::data_write_write(data);
while csr::converter_spi::pending_read() != 0 {}
while csr::converter_spi::active_read() != 0 {}
}
Ok(())
}
unsafe {
csr::converter_spi::data_write_write(data);
while csr::converter_spi::pending_read() != 0 {}
while csr::converter_spi::active_read() != 0 {}
}
Ok(())
}
#[cfg(has_converter_spi)]
pub fn read(busno: u8) -> Result<u32, ()> {
if busno != 0 {
return Err(())
pub fn read(busno: u8) -> Result<u32, ()> {
if busno != 0 {
return Err(())
}
Ok(unsafe {
csr::converter_spi::data_read_read()
})
}
Ok(unsafe {
csr::converter_spi::data_read_read()
})
}
#[cfg(not(has_converter_spi))]
pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
#[cfg(not(has_converter_spi))]
pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8) -> Result<(), ()> { Err(()) }
#[cfg(not(has_converter_spi))]
pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
#[cfg(not(has_converter_spi))]
pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
mod imp {
pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8)
-> Result<(), ()> { Err(()) }
pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
}
pub use self::imp::*;

6
artiq/firmware/runtime/lib.rs
View File

@ -56,7 +56,7 @@ fn startup() {
info!("gateware version {}", board::ident::read(&mut [0; 64]));
#[cfg(has_serwb_phy_amc)]
board::serwb::wait_init();
board_artiq::serwb::wait_init();
let t = board::clock::get_ms();
info!("press 'e' to erase startup and idle kernels...");
@ -75,9 +75,9 @@ fn startup() {
#[cfg(si5324_free_running)]
setup_si5324_free_running();
#[cfg(has_hmc830_7043)]
board::hmc830_7043::init().expect("cannot initialize HMC830/7043");
board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
#[cfg(has_ad9154)]
board::ad9154::init().expect("cannot initialize AD9154");
board_artiq::ad9154::init().expect("cannot initialize AD9154");
#[cfg(has_ethmac)]
startup_ethernet();