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36 Commits (14fa038118884f807c4680c128a12b0148ca7fd5)

Author SHA1 Message Date
morgan 7827c7b803 Gateware: kasli_soc WRPLL setup 
kasli_soc: use enable_wrpll from json to switch from si5324 to si549
kasli_soc: add wrpll for all variants
kasli_soc: add gtx & main tag nFIQ for all variants
kasli_soc: add clk_synth_se for master & satellite
kasli_soc: add wrpll_refclk for runtime
kasli_soc: add skewtester for satman
kasli_soc: add WRPLL_REF_CLK config for firmware
 2024-04-11 15:18:10 +08:00
linuswck e1b2c45813 kasli_soc & zc706: Fix GTX Clock Path during INIT 2023-11-07 18:55:08 +08:00
Egor Savkin b768d5648c Add grabber module 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-10-16 14:35:20 +08:00
linuswck 136e24f597 kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 
- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
 2023-10-11 16:45:26 +08:00
linuswck b15322b6ba kasli_soc: Add support for shuttler on gateware 
- Port from artiq repo
- Add EEM_DRTIO gateware
 2023-10-10 11:22:05 +08:00
mwojcik 49205eea17 satellite gateware: add kernel rtio to cri 2023-10-09 11:36:23 +08:00
sven-oxionics 656cbf4546 kasli_soc: use sed_lanes value from HW description 
https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
 2023-10-06 15:37:56 +01:00
mwojcik ae3099dd8e kasli_soc: support 100MHz clock 2023-10-06 16:27:25 +08:00
morgan 1ccae0d442 consolidate all `write..file()` into `config.py` 2023-09-11 11:48:19 +08:00
MorganTL 0e6309b95e change write_rustc_cfg_file to follow artiq repo 2023-08-30 14:56:12 +08:00
morgan 622d267d55 add virtual LEDs, improve IO expander setup, drive TX_DISABLE 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-08-28 16:08:10 +08:00
linuswck 4ae8557018 drtio: remame drtio_transceiver to gt_drtio 
Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
 2023-08-28 13:05:40 +08:00
Sebastien Bourdeauducq ca17cd419e Revert "kasli_soc: add SFP0..3 LED indication" 
This reverts commit 5111778363.
 2023-08-03 10:42:09 +08:00
morgan 5111778363 kasli_soc: add SFP0..3 LED indication 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-07-24 16:30:14 +08:00
Sebastien Bourdeauducq ee438105b2 json: base -> drtio_role 2023-06-16 17:03:25 +08:00
Denis Ovchinnikov 63594d7e3d update configuration of IBUFDS_GTE2 
Input clock is terminated internally with 50 Ohm on each leg and to 4/5 MGTAVCC.
 2023-05-30 12:08:41 +08:00
mwojcik c536a70890 satellite gateware: add rtio analyzer 2023-05-22 15:23:24 +08:00
mwojcik 4b1ce1a6ff satellites: add rtio_dma, connect as cri master 2023-03-21 15:54:58 +08:00
mwojcik dce37a52aa KasliSoC satellite: fix serdes timing 2023-02-20 13:07:42 +08:00
mwojcik 46b2687d70 RTIO/SYS Clock merge 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-02-17 15:52:43 +08:00
mwojcik 19e60073de kasli_soc: ident = variant name 2022-10-21 11:55:24 +08:00
mwojcik def4d989cd kasli_soc: fix si5324 pins routed to GTX 2022-04-25 12:33:21 +08:00
mwojcik 3cf86a6335 satellites: add rtio_crg cfg 2022-04-12 13:44:53 +08:00
occheung a22b13cc46 kasli_soc: forward SMA clkin 2022-03-09 12:43:47 +08:00
spaqin 85e5c08d7f kasli_soc: use si5324 in master 2022-03-04 13:17:53 +08:00
mwojcik 31fb2b388a Support for DRTIO 100MHz (#155) 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-12-03 17:19:42 +08:00
mwojcik 8be5048cd3 upgrade to new clock configuration system (#152) 
As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.

Reviewed-on: #152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-11-29 11:17:59 +08:00
Sebastien Bourdeauducq 4fa824f42b kasli-soc: remove irrelevant comment 2021-10-08 16:13:17 +08:00
mwojcik ab0c205dd2 gateware: add DRTIO 
Reviewed-on: #140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-10-08 16:12:30 +08:00
mwojcik e3d3cb2311 si5324: bring on par with mainline ARTIQ (#132) 
si5324 driver in runtime should be now equal in function to the one in artiq.

kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.

Reviewed-on: #132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-08-04 09:12:38 +08:00
Sebastien Bourdeauducq 8128dc0b56 Revert "kasli-soc: work around I2C breakage (#130)" 
This reverts commit f1fd55dee5.
 2021-07-30 16:55:06 +08:00
Sebastien Bourdeauducq 852123b42a kasli-soc: add RTIO LEDs 2021-05-30 20:40:53 +08:00
Sebastien Bourdeauducq f1fd55dee5 kasli-soc: work around I2C breakage (#130) 2021-05-29 17:13:41 +08:00
Sebastien Bourdeauducq 8815f76114 kasli_soc: fix has_grabber 2021-02-15 21:41:02 +08:00
Sebastien Bourdeauducq ef18fa4c6d kasli_soc: add RTIO log channel
Hydra zc706-hitl-tests Hydra build #129170 of artiq:zynq:zc706-hitl-tests Details
2021-02-15 19:56:59 +08:00
Sebastien Bourdeauducq faf9714e10 add demo build for Kasli-SoC
Hydra zc706-hitl-tests Hydra build #129124 of artiq:zynq:zc706-hitl-tests Details
2021-02-15 19:52:13 +08:00