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548 Commits 5 Branches 0 Tags 2 MiB
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30 Commits

Author SHA1 Message Date
mwojcik d3152f3d24 changed auxctrl tx/rx memory to axi2csr_sram 2021-09-10 15:25:05 +02:00
mwojcik 9c14694fc4 added rtioclockmultiplier where applicable 
(nist variants don't compile for other reasons now)
 2021-09-07 15:22:01 +02:00
mwojcik 1bddad6ff2 kasli_soc: fixes to make satellite variant work 2021-09-07 14:51:46 +02:00
mwojcik 76929d2aa1 zc706: 
* broke down platforms (refactor),
* added nist master/sat variants
* master doesn't build yet, satellite only simple variant
 2021-09-06 14:30:09 +02:00
mwojcik 20681a13c4 gateware: fixed cfg keys - case consistent w/ code 2021-09-06 10:57:42 +02:00
mwojcik 9022064cf1 added siphaser to zc706 satellite, small fixes 2021-09-06 09:06:16 +02:00
mwojcik b678408105 rustc_cfg is case sensitive. Si5324 was not achnowledged. 2021-09-03 14:58:17 +02:00
mwojcik 37e8b576b1 satellite: 
* fixing repeaters that can't exist on zc706
* fixing various warnings
* fixed timer and i2c references
 2021-08-31 15:25:56 +02:00
mwojcik ff7ba56d26 forgot to remove a debug print 2021-08-26 12:54:19 +02:00
mwojcik b585eaaa37 zc706: added memory iface generator 2021-08-24 13:51:38 +02:00
mwojcik 1358c8bfe9 zc706 gateware: base class for drtio is SoCCore 2021-08-24 12:01:04 +02:00
mwojcik 7b868e1c9d few fixes, typos and missed unnecessary statements 2021-08-17 13:16:02 +02:00
mwojcik 7ff59f57a9 gateware: updated gtx interface 2021-08-10 15:11:21 +02:00
mwojcik 118893c0b2 disabled adding axi slave/mem 
drtioauxcontroller uses AXI rather than Wishbone
still won't compile - unresolved clock domain error
 2021-08-06 15:25:59 +02:00
mwojcik ae86bbb76e zc706 gateware fixes: 
replaced crg cd_sys.clk with ps7.cd_sys.clk
restored gpio
removed mentions of i2c
user_sma_clock consumed by _RTIOCRG already
 2021-08-06 13:31:16 +02:00
mwojcik d68cf7dd49 gateware: replaced wb slave w/ axi (diff soccore) 2021-08-06 11:05:49 +02:00
mwojcik f9860a61b7 sys_clk_freq is actually 125mhz 2021-08-06 10:39:37 +02:00
mwojcik 97dfa07bdb determined probable sys_clk_freq for GTX transcvr 2021-08-06 10:05:04 +02:00
mwojcik b2dd68bd92 removed unnecessary and wrong add_drtio 2021-08-03 09:52:50 +02:00
mwojcik cafbe97e47 zc706: added targets to default.nix, fixed wrong base cls 2021-07-30 15:14:40 +02:00
mwojcik 0ce86317c9 zc706: added rough master/satellite drtio support 2021-07-29 15:38:23 +02:00
Sebastien Bourdeauducq 506c741238 support absence of gateware RTIO clock selection mux 2021-02-15 21:41:30 +08:00
Sebastien Bourdeauducq 1e20259c36 fix acpki selection 2020-08-04 13:26:45 +08:00
Sebastien Bourdeauducq f8d4036451 add ACP kernel initiator 
Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55

Work-in-progress, only gateware part and build system, untested.
 2020-08-04 13:15:26 +08:00
Sebastien Bourdeauducq 523524c319 zc706: add RTIO log channels 2020-07-19 14:05:35 +08:00
Sebastien Bourdeauducq f69e41af5e gateware: fix VADJ I/O standard conflict 2020-07-16 17:58:31 +08:00
Sebastien Bourdeauducq 6a361893c2 gateware: make LEDs common to all variants 
Makes quick testing easier.
 2020-07-16 17:36:27 +08:00
Sebastien Bourdeauducq 8e758ecc17 add RTIO analyzer core (untested) 2020-07-15 23:06:34 +08:00
Sebastien Bourdeauducq a7073edf79 add DMA core (untested) 2020-07-13 10:37:17 +08:00
Sebastien Bourdeauducq e3ff21b1b5 create gateware folder 2020-07-11 17:49:54 +08:00