9 Commits

Author	SHA1	Message	Date
mwojcik	7b868e1c9d	few fixes, typos and missed unnecessary statements	2021-08-17 13:16:02 +02:00
mwojcik	61f81cec47	sram: redesigned write FSM. removed unused signals	2021-08-17 11:10:08 +02:00
mwojcik	3e1d14ff38	replaced increment logic with ready Incr module	2021-08-16 15:33:50 +02:00
mwojcik	67ed7fae78	sram: or operator in wrong place for wrapped burst	2021-08-16 12:05:23 +02:00
mwojcik	f015d6732b	sram: support for different burst settings on read	2021-08-16 11:51:50 +02:00
mwojcik	b6dd5bea68	sram: fixed wrong assumptions on some signals	2021-08-13 14:58:18 +02:00
mwojcik	bfe0c34f57	sram: rewrote read fsm for sram	2021-08-13 14:14:43 +02:00
mwojcik	39509f01d6	aux_controller: sram ported to axi, first attempt	2021-08-13 13:06:10 +02:00
mwojcik	066987bf07	aux_controller: started porting from wb to axi	2021-08-11 14:34:44 +02:00