8be5048cd3
upgrade to new clock configuration system ( #152 )
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As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.
Reviewed-on: M-Labs/artiq-zynq#152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-11-29 11:17:59 +08:00
0b27349ec4
dummy_spi -> pmod_spi
2021-10-14 16:37:13 +08:00
21eb1cab1a
zc706: added dummy spi in place of sdio
2021-10-14 15:43:51 +08:00
3096daaaee
zc706: removed nist_clock sdcard, put pmod instead
2021-10-14 15:01:38 +08:00
4fbfccf575
zc706: fix nist_qc2 extension, ams101 iostandard
2021-10-14 12:39:09 +08:00
5c40115945
make ZC706 RTIO channels consistent with KC705
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Reviewed-on: M-Labs/artiq-zynq#147
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-13 17:20:25 +08:00
d04a7decfe
removed simple variants from zc706
2021-10-08 11:07:12 +02:00
4fa824f42b
kasli-soc: remove irrelevant comment
2021-10-08 16:13:17 +08:00
ab0c205dd2
gateware: add DRTIO
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Reviewed-on: M-Labs/artiq-zynq#140
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-10-08 16:12:30 +08:00
18e05c91e1
zc706: si5324 is not needed for standalone target
2021-08-04 09:14:19 +08:00
e3d3cb2311
si5324: bring on par with mainline ARTIQ ( #132 )
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si5324 driver in runtime should be now equal in function to the one in artiq.
kasli-soc has no way of doing a hard reset on the peripheral, but zc706 does.
Reviewed-on: M-Labs/artiq-zynq#132
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
2021-08-04 09:12:38 +08:00
8128dc0b56
Revert "kasli-soc: work around I2C breakage ( #130 )"
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This reverts commit f1fd55dee5
2021-07-30 16:55:06 +08:00
852123b42a
kasli-soc: add RTIO LEDs
2021-05-30 20:40:53 +08:00
f1fd55dee5
kasli-soc: work around I2C breakage ( #130 )
2021-05-29 17:13:41 +08:00
506c741238
support absence of gateware RTIO clock selection mux
2021-02-15 21:41:30 +08:00
8815f76114
kasli_soc: fix has_grabber
2021-02-15 21:41:02 +08:00
ef18fa4c6d
kasli_soc: add RTIO log channel
2021-02-15 19:56:59 +08:00
faf9714e10
add demo build for Kasli-SoC
2021-02-15 19:52:13 +08:00
8d4e42be32
remove redpitaya and coraz7 support
2021-02-15 19:30:13 +08:00
4039431533
kasli_soc: fix eem iostandards
2021-02-07 22:34:29 +08:00
3f9bd06468
add Kasli-SoC generic gateware builder (WIP)
2021-02-07 14:44:32 +08:00
32048ead20
gateware/coraz7: remove unused VARIANTS
2020-11-14 02:24:29 +01:00
113c8eb0b8
add coraz7 + redpitaya targets
2020-11-13 20:17:18 +01:00
03d9827a5a
acpki: working
2020-09-09 21:24:49 +08:00
537f4968eb
acpki: add legacy i_status/o_status registers
2020-08-04 17:31:35 +08:00
62988a580e
acpki: update for combined RTIO channel/address
2020-08-04 17:28:15 +08:00
1e20259c36
fix acpki selection
2020-08-04 13:26:45 +08:00
f8d4036451
add ACP kernel initiator
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Based on work by Chris Ballance
https://github.com/m-labs/artiq/issues/1167#issuecomment-427188287
M-Labs/artiq-zynq#55
Work-in-progress, only gateware part and build system, untested.
2020-08-04 13:15:26 +08:00
59cf2764ce
dma: report AXI bus error
2020-07-21 12:47:20 +08:00
21135c6a41
analyzer: report AXI bus errors
2020-07-20 19:51:22 +08:00
523524c319
zc706: add RTIO log channels
2020-07-19 14:05:35 +08:00
f69e41af5e
gateware: fix VADJ I/O standard conflict
2020-07-16 17:58:31 +08:00
6a361893c2
gateware: make LEDs common to all variants
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Makes quick testing easier.
2020-07-16 17:36:27 +08:00
ae7ca22db9
dma: fix endianness issues
2020-07-16 17:27:08 +08:00
10a12245a3
analyzer: fix endianness issue
2020-07-16 17:10:09 +08:00
0c6db0d12c
analyzer: use 32-bit byte_count
2020-07-16 11:36:04 +08:00
0b0ca8de49
analyzer: drive wid and wstrb
2020-07-15 23:11:19 +08:00
8e758ecc17
add RTIO analyzer core (untested)
2020-07-15 23:06:34 +08:00
b68cb137e5
dma: style
2020-07-15 23:06:14 +08:00
12ba867268
dma: fix and cleanup test
2020-07-13 18:58:08 +08:00
5c3c3c26b5
dma: fix inflight_cnt and eop generation
2020-07-13 18:51:55 +08:00
ea96cf96d3
dma: add simulation test (WIP)
2020-07-13 12:04:10 +08:00
10888cc6c6
dma: remove unneeded import
2020-07-13 10:42:02 +08:00
a7073edf79
add DMA core (untested)
2020-07-13 10:37:17 +08:00
e3ff21b1b5
create gateware folder
2020-07-11 17:49:54 +08:00
