forked from M-Labs/artiq-zynq
dummy_spi -> pmod_spi
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21eb1cab1a
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0b27349ec4
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@ -106,8 +106,8 @@ _ams101_dac = [
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)
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]
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_dummy_spi = [
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("dummy_spi", 0,
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_pmod_spi = [
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("pmod_spi", 0,
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# PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
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Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
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Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
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@ -467,7 +467,7 @@ class _NIST_CLOCK_RTIO:
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platform.add_extension(leds_fmc33)
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platform.add_extension(pmod1_33)
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platform.add_extension(_ams101_dac)
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platform.add_extension(_dummy_spi)
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platform.add_extension(_pmod_spi)
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rtio_channels = []
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@ -516,7 +516,7 @@ class _NIST_CLOCK_RTIO:
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phy, ififo_depth=128))
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# no SDIO on PL side, dummy SPI placeholder instead
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phy = spi2.SPIMaster(platform.request("dummy_spi"))
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phy = spi2.SPIMaster(platform.request("pmod_spi"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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