temp debug bisect

experiments/src/main.rs

@@ -6,6 +6,7 @@ extern crate alloc;
 
 use alloc::collections::BTreeMap;
 use core::arch::asm;
+use core::ptr::addr_of_mut;
 use libasync::{
     delay,
     smoltcp::{Sockets, TcpStream},
@@ -70,7 +71,7 @@ interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
             if id.0 == 0 {
                 gic.end_interrupt(id);
                 asm::exit_irq();
-                SP.write(&mut __stack1_start as *mut _ as u32);
+                SP.write(addr_of_mut!(__stack1_start) as *mut _ as u32);
                 asm::enable_irq();
                 CORE1_RESTART.store(false, Ordering::Relaxed);
                 notify_spin_lock();

libboard_zynq/src/eth/mod.rs

@@ -350,6 +350,7 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
 
 impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
     pub fn start_rx(self, rx_size: usize) -> Eth<GEM, rx::DescList, TX> {
+        info!("rx bisect 0");
         let new_self = Eth {
             rx: rx::DescList::new(rx_size),
             tx: self.tx,
@@ -357,15 +358,20 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
             phy: self.phy,
             idle: self.idle,
         };
+        info!("rx bisect 1");
         let list_addr = new_self.rx.list_addr();
+        info!("rx bisect 2");
         assert!(list_addr & 0b11 == 0);
+        info!("rx bisect 3");
         GEM::regs().rx_qbar.write(
             regs::RxQbar::zeroed()
                 .rx_q_baseaddr(list_addr >> 2)
         );
+        info!("rx bisect 4");
         GEM::regs().net_ctrl.modify(|_, w|
             w.rx_en(true)
         );
+        info!("rx bisect 5");
         new_self
     }
 

libboard_zynq/src/eth/rx.rs

@@ -2,6 +2,7 @@ use core::ops::Deref;
 use alloc::{vec, vec::Vec};
 use libcortex_a9::{asm::*, cache::*, UncachedSlice};
 use libregister::*;
+use log::info;
 use super::Buffer;
 
 #[derive(Debug)]
@@ -63,27 +64,35 @@ pub struct DescList {
 
 impl DescList {
     pub fn new(size: usize) -> Self {
+        info!("desc list bisect 0");
         let mut list = UncachedSlice::new(size, || DescEntry::zeroed())
             .unwrap();
+        info!("desc list bisect 1");
         let mut buffers = vec![Buffer::new(); size];
 
+        info!("desc list bisect 2");
         let last = list.len().min(buffers.len()) - 1;
+        info!("desc list bisect 3");
         for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
             let is_last = i == last;
             let buffer_addr = &mut buffer.0[0] as *mut _ as u32;
             assert!(buffer_addr & 0b11 == 0);
+            info!("desc list bisect 4");
             entry.word0.write(
                 DescWord0::zeroed()
                     .used(false)
                     .wrap(is_last)
                     .address(buffer_addr >> 2)
             );
+            info!("desc list bisect 5");
             entry.word1.write(
                 DescWord1::zeroed()
             );
+            info!("desc list bisect 6");
             // Flush buffer from cache, to be filled by the peripheral
             // before next read
             dcci_slice(&buffer[..]);
+            info!("desc list bisect 7");
         }
 
         DescList {

libconfig/src/lib.rs

@@ -189,10 +189,10 @@ impl Config {
             if is_str {
                 let mut f = root_dir.create_file("/CONFIG.TXT")?;
                 f.seek(SeekFrom::End(0))?;
-                f.write(key.as_bytes());
+                f.write(key.as_bytes())?;
-                f.write("=".as_bytes());
+                f.write("=".as_bytes())?;
-                f.write(value.as_slice());
+                f.write(value.as_slice())?;
-                f.write(NEWLINE);
+                f.write(NEWLINE)?;
             } else {
                 let dir = root_dir.create_dir("/CONFIG")?;
                 let mut f = dir.create_file(&[key, ".BIN"].concat())?;

libcortex_a9/src/mmu.rs

@@ -1,4 +1,5 @@
 use bit_field::BitField;
+use core::ptr::addr_of_mut;
 use super::{regs::*, asm::*, cache::*};
 use libregister::RegisterW;
 
@@ -136,7 +137,7 @@ pub struct L1Table {
 impl L1Table {
     pub fn get() -> &'static mut Self {
         unsafe {
-            &mut L1_TABLE
+            &mut *addr_of_mut!(L1_TABLE)
         }
     }
 

libcortex_a9/src/sync_channel.rs

@@ -37,7 +37,7 @@ impl<'a, T> Sender<'a, T> where T: Clone {
             notify_spin_lock();
             if !prev.is_null() {
                 unsafe {
-                    Box::from_raw(prev);
+                    drop(Box::from_raw(prev));
                 }
             }
             Ok(())
@@ -91,7 +91,7 @@ impl<'a, T> Sender<'a, T> where T: Clone {
         for v in self.list.iter() {
             let original = v.swap(core::ptr::null_mut(), Ordering::Relaxed);
             if !original.is_null() {
-                Box::from_raw(original);
+                drop(Box::from_raw(original));
             }
         }
     }

libcortex_a9/src/uncached.rs

@@ -1,5 +1,6 @@
 use core::{
-    mem::{align_of, size_of}, ops::{Deref, DerefMut}, panic
+    ops::{Deref, DerefMut},
+    mem::{align_of, size_of},
 };
 use alloc::alloc::{dealloc, Layout, LayoutError};
 use crate::mmu::{L1_PAGE_SIZE, L1Table};
@@ -19,6 +20,7 @@ impl<T> UncachedSlice<T> {
         let layout = Layout::from_size_align(size, align)?;
         let ptr = unsafe { alloc::alloc::alloc(layout).cast::<T>() };
         let start = ptr as usize;
+        assert_eq!(start & (L1_PAGE_SIZE - 1), 0);
 
         for page_start in (start..(start + size)).step_by(L1_PAGE_SIZE) {
             // non-shareable device
@@ -29,7 +31,10 @@ impl<T> UncachedSlice<T> {
                     l1_section.bufferable = false;
                 });
         }
+
         let slice = unsafe { core::slice::from_raw_parts_mut(ptr, len) };
+        // verify size
+        assert!(unsafe { slice.get_unchecked(len) } as *const _ as usize <= start + size);
         // initialize
         for e in slice.iter_mut() {
             *e = default();

libsupport_zynq/src/boot.rs

@@ -1,5 +1,5 @@
 use r0::zero_bss;
-use core::ptr::write_volatile;
+use core::ptr::{write_volatile, addr_of_mut, addr_of};
 use core::arch::asm;
 use libregister::{
     VolatileCell,
@@ -43,7 +43,7 @@ unsafe extern "C" fn boot_core0() -> ! {
     let mpcore = mpcore::RegisterBlock::mpcore();
     mpcore.scu_invalidate.invalidate_all_cores();
 
-    zero_bss(&mut __bss_start, &mut __bss_end);
+    zero_bss(addr_of_mut!(__bss_start), addr_of_mut!(__bss_end));
 
     let mmu_table = mmu::L1Table::get()
         .setup_flat_layout();
@@ -132,7 +132,9 @@ impl Core1 {
             CORE1_ENABLED.set(true);
         }
         // Flush cache-line
-        cache::dcc(unsafe { &CORE1_ENABLED });
+        unsafe {
+            cache::dcc(&*addr_of!(CORE1_ENABLED) );
+        }
         if sdram {
             cache::dccmvac(0);
             asm::dsb();
@@ -153,7 +155,7 @@ impl Core1 {
     pub fn disable(&self) {
         unsafe {
             CORE1_ENABLED.set(false);
-            cache::dccmvac(&CORE1_ENABLED  as *const _ as usize);
+            cache::dccmvac(addr_of!(CORE1_ENABLED) as *const _ as usize);
             asm::dsb();
         }
         self.restart();

szl/src/main.rs

@@ -8,6 +8,7 @@ mod netboot;
 
 use alloc::rc::Rc;
 use core::mem;
+use core::ptr::{addr_of_mut, addr_of};
 use libboard_zynq::{
     self as zynq,
     clocks::source::{ArmPll, ClockSource, IoPll},
@@ -115,18 +116,18 @@ pub fn main_core0() {
 
     unsafe {
         let max_len =
-            &__runtime_end as *const usize as usize - &__runtime_start as *const usize as usize;
+            addr_of!(__runtime_end) as *const usize as usize - addr_of!(__runtime_start) as *const usize as usize;
         match slcr::RegisterBlock::unlocked(|slcr| slcr.boot_mode.read().boot_mode_pins()) {
             slcr::BootModePins::Jtag => netboot::netboot(
                 &mut bootgen_file,
                 config,
-                &mut __runtime_start as *mut usize as *mut u8,
+                addr_of_mut!(__runtime_start) as *mut usize as *mut u8,
                 max_len,
             ),
             slcr::BootModePins::SdCard => {
                 if boot_sd(
                     &mut bootgen_file,
-                    &mut __runtime_start as *mut usize as *mut u8,
+                    addr_of_mut!(__runtime_start) as *mut usize as *mut u8,
                     max_len,
                 )
                 .is_err()
@@ -136,7 +137,7 @@ pub fn main_core0() {
                     netboot::netboot(
                         &mut bootgen_file,
                         config,
-                        &mut __runtime_start as *mut usize as *mut u8,
+                        addr_of_mut!(__runtime_start) as *mut usize as *mut u8,
                         max_len,
                     )
                 }
@@ -147,7 +148,7 @@ pub fn main_core0() {
                 netboot::netboot(
                     &mut bootgen_file,
                     config,
-                    &mut __runtime_start as *mut usize as *mut u8,
+                    addr_of_mut!(__runtime_start) as *mut usize as *mut u8,
                     max_len,
                 )
             }