Commit Graph

7192 Commits

Author SHA1 Message Date
3a21794b79 nix: update user instructions 2019-02-10 01:01:16 +08:00
f673ce276f nix: consistent naming of board artifacts 2019-02-09 18:55:50 +08:00
8194f74252 nix: build board conda package 2019-02-09 18:06:36 +08:00
7c6abfb2ce nix: cleanup 2019-02-09 17:58:46 +08:00
ee611c5c30 nix: build gateware 2019-02-09 15:07:16 +08:00
2aab84453d nix: commit missing file 2019-02-09 14:44:32 +08:00
a52234b5ff nix: build firmware on hydra 2019-02-09 14:29:37 +08:00
13c4d935a2 nix/artiq-board: build tester variant 2019-02-09 14:23:36 +08:00
e424927049 nix: use nixpkgs cargo
This simplifies the code and avoids multiplication of cargo versions.
This installs cargo 1.27, but it is compatible enough with artiq rustc
1.28 not to cause any problems for our purposes.
2019-02-09 14:19:34 +08:00
7584639acd nix/artiq-board: cleanup 2019-02-09 13:41:16 +08:00
07ac42505b nix: add firmware derivation (WIP) 2019-02-09 10:36:20 +08:00
f0f50bf1dc nix: cleanup 2019-02-09 10:24:22 +08:00
2de1eaa521 dashboard: reconnect to core moninj
* handle disconnects like core device address changes and do a
  disconnect/connect iteration
* after connection failure wait 10 seconds and try again
* this addresses the slight regression from release-2
  to release-3 where the moninj protocol was made stateful
  (#838 and #1125)
* it would be much better to fix smoltcp/runtime to no loose the
  connection under pressure (#1125)
* the crashes reported in #838 look more like a race condition
* master disconnects still require dashboard restarts

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-02-08 23:52:16 +08:00
7994c294af nix: set up hydra to provide conda package 2019-02-08 23:14:32 +08:00
1cfd26dc2e kasli: add UNSW variant 2019-02-08 17:51:51 +08:00
306d9cf5d0 nix: work around lack of PYTHON environment variable in conda build 2019-02-08 15:50:24 +08:00
744ef03fa1 conda: remove --install-lib workaround 2019-02-08 15:50:02 +08:00
6f1bb5c351 nix: add experimental derivation to build conda package deterministically 2019-02-08 15:23:31 +08:00
3e8fe3f29d suservo: fix permissions 2019-02-08 14:54:02 +08:00
David Nadlinger
ef934ad958 Add test/release notes for command-less controllers
See eaa1b44b00 for the actual change.
2019-02-07 21:51:15 +00:00
eaa1b44b00 ctlmgr: ignore controllers without a "command" field
Allow controllers to be specified without a "command" field. The user takes
responsibility for ensuring the controller is running: the controller manager
does not attempt to ping the controller. This is useful when one has a common
controller shared between several masters.
2019-02-07 21:50:29 +00:00
hartytp
0ebff04ad7 SUServo: apply bit masks to servo memory writes to prevent overflows
Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 17:04:11 +01:00
hartytp
f6142816b8
Revert "SUServo: remove references to non-existent a0 parameter" (#1270)
This reverts commit f3aab2b89156bbc1b12f847093a87a8933293df2.

Signed-off-by: TPH <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:57:43 +00:00
hartytp
fe63c9b366
SUServo: remove references to non-existent a0 parameter (#1268)
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:29:32 +00:00
hartytp
df6c1fca2c
SUServo: flake8 [NFC] (#1267)
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 15:13:44 +00:00
hartytp
87e85bcc14 suservo: fix coefficient data writing
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 14:47:11 +01:00
whitequark
d6eb2b023a compiler: monomorphize casts first, but more carefully.
This reverts 425cd7851, which broke the use of casts to define
integer width.

Instead of it, two steps are taken:
  * First, literals are monomorphized, leading to predictable result.
  * Second, casts are monomorphized, in a top-bottom way. I.e.
    consider the expression `int64(round(x))`. If round() was visited
    first, the intermediate precision would be 32-bit, which is
    clearly undesirable. Therefore, contextual rules should take
    priority over non-contextual ones.

Fixes #1252.
2019-02-07 06:24:32 +00:00
David Nadlinger
0da799fa46 conda: Require recent aiohttp
artiq_influxdb doesn't work with aiohttp 0.17 (anymore), as the
ClientSession API changed. I have not looked up precisely which
is the first version that works, but 3.x has been out for almost
a year and is available on the Anaconda/conda-forge channels.
2019-02-06 23:39:32 +00:00
b56c7cec1e kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
d0b6f92b11 nix: bump jesd204b 2019-02-04 19:31:09 +08:00
2f7364563c nix: fix breakage introduced by nixpkgs 6f05dea3 2019-02-04 19:28:36 +08:00
5a7460a38e kasli: add sync delays to device_db_berkeley 2019-02-01 22:14:03 +08:00
ea431b6982 sayma_rtm: use 150MHz RTIO freq for DDMTD 2019-01-31 20:43:44 +08:00
ec230d6560 sayma: move SYSREF DDMTD to the RTM
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
8119000982 sayma_rtm_drtio: use Si5324 soft reset
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.

Allows using Si5324 + HMC7043 chips at the same time.

Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
2019-01-31 19:43:54 +08:00
82106dcd95 si5324: add bypass function 2019-01-31 19:38:55 +08:00
8bbd4207d8 si5324: use consistent bitmask 2019-01-31 19:35:56 +08:00
bdb6678cec nix: bump migen 2019-01-31 15:13:17 +08:00
d3c608aaec jesd204sync: reset and check lock status of DDMTD helper PLL in firmware 2019-01-31 15:11:16 +08:00
fa3b40141d hmc830_7043: document sayma clock muxes 2019-01-31 15:10:11 +08:00
ec8560911f siphaser: bugfixes
* Fix integer overflow in degree computation
* Add some phase slips after the first transition to get out of the jitter zone and avoid intermittent short windows
2019-01-30 16:56:38 +08:00
c591009220 sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
9d0d02a561 jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target
There is plenty of slack (it only needs to meet timing at the RTIO frequency).
2019-01-29 16:48:55 +08:00
ed6aa29897 jesd204sync: print more information on test_slip_ddmtd error 2019-01-29 16:47:29 +08:00
2e8decbce3 kasli_sawgmaster: generate a HMC830 clock with Urukul 2019-01-29 15:06:45 +08:00
9ae57fd51e sayma: pass rtio_clk_freq to DDMTD core 2019-01-29 15:06:45 +08:00
90c9fa446f test: add array transfer test
200 kB/s, more than a factor of 10 slower than the bare string transfer

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-01-28 14:30:44 +00:00
7a5d28b73d jesd204sync: test SYSREF period 2019-01-28 19:11:38 +08:00
1a42e23fb4 jesd204sync: print DDMTD SYSREF final alignment delta 2019-01-28 18:39:16 +08:00
eebff6d77f jesd204sync: fix max_phase_deviation 2019-01-28 18:38:18 +08:00