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18d18b6685
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phaser: add sync ttl input for monitoring
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2016-10-10 17:13:23 +02:00 |
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4d87f0e9e0
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phaser: instantiate jesd204b core, wire up
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2016-10-06 14:44:22 +02:00 |
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c54b6e2f3c
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phaser: add README
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2016-10-05 19:24:34 +02:00 |
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4a0eaf0f95
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phaser: add jesd204b rtio dds
gateware: add jesd204b awg
gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce
sawg: kernel support and docs
sawg: coredevice api fixes
sawg: example ddb/experiment
phaser: add conda package
examples/phaser: typo
sawg: adapt tests, fix accu stb
sawg: tweak dds parameters
sawg: move/adapt/extend tests
sawg: test phy, refactor
phaser: non-rtio spi
phaser: target cli update
phaser: ad9154-fmc-ebz pins
phaser: reorganize fmc signal naming
phaser: add test mode stubs
phaser: txen is LVTTL
phaser: clk spi xfer test
phaser: spi for ad9154 and ad9516
phaser: spi tweaks
ad9154: add register map from ad9144.xml
ad9516: add register map from ad9517.xml and manual adaptation
ad9154_reg: just generate getter/setter macros as well
ad9154: reg WIP
ad9154: check and fix registers
kc705: single ended rtio_external_clk
use single ended user_sma_clk_n instead of p/n to free up one clock sma
kc705: mirror clk200 at user_sma_clock_p
ad9516_regs.h: fix B_COUNTER_MSB
phase: wire up clocking differently
needs patched misoc
kc705: feed rtio_external_clock directly
kc705: remove rtio_external_clk for phaser
phaser: spi tweaks
ad9516: some startup
ad9516_reg fixes
phaser: setup ad9516 for supposed 500 MHz operation
ad9516: use full duplex spi
ad9154_reg: add CONFIG_REG_2
ad9154_reg: fixes
phaser: write some ad9154 config
ad9154_reg: fixes
ad9154: more init, and human readable setup
ad9154/ad9516: merge spi support
ad9154: status readout
Revert "kc705: remove rtio_external_clk for phaser"
This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.
Revert "kc705: feed rtio_external_clock directly"
This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.
Revert "phase: wire up clocking differently"
This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.
Revert "kc705: mirror clk200 at user_sma_clock_p"
This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.
Revert "kc705: single ended rtio_external_clk"
This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.
ad9516: 2000 MHz clock
phaser: test clock dist
phaser: test freqs
ad9154: iostandards
phaser: drop clock monitor
phaser: no separate i2c
phaser: drive rtio from refclk, wire up sysref
phaser: ttl channel for sync
ad9154: 4x interp, status, tweaks
phaser: sync/sysref 33V banks
phaser: sync/sysref LVDS_25 inputs are VCCO tolerant
phaser: user input-only ttls
phaser: rtio fully from refclk
ad9154: reg name usage fix
ad9154: check register modifications
Revert "ad9154: check register modifications"
This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.
ad9154: fix status code
ad9154: addrinc, recal serdes pll
phaser: coredevice, example tweaks
sawg: missing import
sawg: type fixes
ad9514: move setup functions
ad9154: msb first also decreasing addr
phaser: use sys4x for rtio internal ref
phaser: move init code to main
phaser: naming cleanup
phaser: cleanup pins
phaser: move spi to kernel cpu
phaser: kernel support for ad9154 spi
ad9154: add r/w methods
ad9154: need return annotations
ad9154: r/w methods are kernels
ad9154_reg: portable helpers
phaser: cleanup startup kernel
ad9154: status test
ad9154: prbs test
ad9154: move setup, document
phaser: more documentation
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2016-10-05 16:17:50 +02:00 |
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4ef5eb2644
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doc: move VADJ, closes #554
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2016-09-09 18:40:58 +08:00 |
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2912515e5c
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doc: add warning about pipistrello current draw
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2016-06-11 10:26:35 -06:00 |
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ca9724f517
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doc: add core device comms details
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2016-06-11 10:01:15 -06:00 |
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e8aadd0a1a
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doc: document common KC705 problems. Closes #450
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2016-06-03 23:20:38 -04:00 |
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dhslichter
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141edb521a
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qc2: swap SPI/TTL, all TTL lines are now In+Out compatible
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2016-05-19 10:42:03 +08:00 |
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dhslichter
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f395a630e0
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Updated qc2 pinouts for SPI and 2x DDS bus, update docs
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2016-04-13 18:38:34 +08:00 |
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05317a9259
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manual: QC2 FMC voltage
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2016-03-31 10:47:16 +08:00 |
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878ab9a39b
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manual: document DDS and SPI RTIO channels
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2016-03-10 22:38:49 +08:00 |
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f0b0b1bac7
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support for multiple DDS buses (untested)
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2016-03-09 17:12:50 +08:00 |
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f33baf339f
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pipistrello: drop ttls on pmod, add leds back in
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2016-03-08 23:34:51 +01:00 |
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f39208c95a
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pipistrello: try with fewer leds/pmod ttl
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2016-03-08 22:10:47 +01:00 |
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104d641c59
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pipistrello: move the spi channel like kc705
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2016-03-08 13:30:05 +01:00 |
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40c1cde2e2
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doc: kc705.clock: add spi bus mappings (closes #321)
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2016-03-08 13:28:32 +01:00 |
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9898cb14db
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doc: add pipistrello spi bus
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2016-03-08 13:18:55 +01:00 |
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e23e91f8ac
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doc: add pipistrello pmod ttl channels
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2016-03-08 13:13:33 +01:00 |
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2770d9c729
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doc: I2C/QC2
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2016-03-05 19:02:03 +08:00 |
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2cc1dfaee3
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kc705: move ttl channels together again, update doc
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2016-03-01 19:40:32 +01:00 |
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5fad570f5e
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targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
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2016-03-01 00:35:26 +08:00 |
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0151ac55ff
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ppp: update documentation
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2016-01-25 12:29:05 -07:00 |
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fa1afb7dd8
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add information about CLOCK hardware
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2016-01-20 21:06:02 -05:00 |
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179c50480f
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frontend: split coretool into coreconfig, corelog and coreanalyzer
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2015-12-24 18:51:11 +08:00 |
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whitequark
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9fc7a42036
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pipistrello: expose LED{1..4} as RTIO channels.
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2015-11-23 18:26:45 +08:00 |
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ef487ee8b0
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doc: more updates for dataset API
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2015-10-13 18:45:04 +08:00 |
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d4f42e33e6
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doc: clarify hw support
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2015-08-21 13:33:23 +08:00 |
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178816243c
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doc/core_device: update, add KC705 QC1 TTL table
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2015-08-18 16:04:27 +08:00 |
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16af80ca3e
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doc: add core device explanation
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2015-08-08 22:59:53 +08:00 |
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c0030406c3
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doc: core device page
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2015-08-08 21:24:13 +08:00 |
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