forked from M-Labs/artiq
targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
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a1e1f2b387
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@ -48,10 +48,8 @@ fmc_adapter_io = [
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Subsignal("n", Pins("LPC:CLK1_M2C_N")),
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IOStandard("LVDS")),
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("la32", 0,
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Subsignal("p", Pins("LPC:LA32_P")),
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Subsignal("n", Pins("LPC:LA32_N")),
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IOStandard("LVDS")),
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("la32_p", 0, Pins("LPC:LA32_P"), IOStandard("LVTTL")),
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("la32_n", 0, Pins("LPC:LA32_N"), IOStandard("LVTTL")),
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("spi", 0,
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Subsignal("clk", Pins("LPC:LA13_N")),
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@ -237,6 +237,10 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("la32_p"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 11
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self.config["DDS_AD9914"] = True
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@ -64,6 +64,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| 19 | LED | Output |
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+--------------------+-----------------------+--------------+
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| 20 | LA32_P | Clock |
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+--------------------+-----------------------+--------------+
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Pipistrello
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@ -74,6 +74,13 @@
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"class": "TTLInOut",
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"arguments": {"channel": 18}
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},
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"ttl_clock_la32_p": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLClockGen",
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"arguments": {"channel": 20}
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},
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"led": {
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"type": "local",
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@ -159,7 +166,7 @@
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"loop_out": "ttl0",
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"loop_in": "ttl3",
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#"loop_clock_out": "TODO",
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"loop_clock_out": "ttl_clock_la32_p",
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"loop_clock_in": "ttl7",
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"pmt": "ttl3",
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