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5047 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq fc0ce310a8 examples: fix dds_test RTIO underflow 2017-02-27 11:45:18 +08:00
Sebastien Bourdeauducq 26654e6a3a moninj: Python-side fixes 2017-02-27 11:45:04 +08:00
Sebastien Bourdeauducq 7481eaff52 moninj: use smaller network buffer 2017-02-27 11:44:29 +08:00
whitequark 88bf7d2233 firmware: specialize protocol read/write functions. 
Before this commit, proto::io::{read,write}_* functions were taking
a &mut {Read,Write}. This means a lot of virtual dispatch.
After this commit, all these functions are specialized for
the specific IO trait.

This could be achieved with just changing the signature from
  fn read_x(reader: &mut Read)
to
  fn read_x<R: Read>(reader: &mut R)
but the functions were also grouped into ReadExt and WriteExt
traits as a refactoring.

Initially, it was expected that the generic traits from
the byteorder crate could be used, but they require endianness
to be specified on every call and thus aren't very ergonomic.
They also lack the equivalent to our read_string and read_bytes.

Thus, it seems fine to just define a slightly different extension
trait.

This also optimized the test_rpc_timing test: 1.7ms→1.2ms.
 2017-02-26 18:24:37 +00:00
whitequark de015b994d compiler: allow dumping the object file with ARTIQ_DUMP_OBJ. 2017-02-26 17:09:21 +00:00
Sebastien Bourdeauducq dff23293c7 Merge branch 'master' of github.com:m-labs/artiq 2017-02-27 01:05:40 +08:00
Sebastien Bourdeauducq 96bf414257 dashboard: use new moninj protocol 2017-02-27 00:59:31 +08:00
Sebastien Bourdeauducq 990b8152f6 coredevice: add moninj protocol driver 2017-02-27 00:59:17 +08:00
whitequark 5d3b00cf12 Implement recording of DMA traces on the core device. 2017-02-26 02:50:20 +00:00
whitequark 3a1f14c16c compiler: fix overly strict constness analysis. 
Before this commit, the following code would fail to compile...
  obj.foo.bar = True
... if foo is marked kernel_invariant in obj, even if bar is not
marked as such in obj.foo.
 2017-02-26 01:58:21 +00:00
whitequark a07bd918f0 firmware: use Rust naming conventions for enum variants. 2017-02-25 22:34:11 +00:00
whitequark 2a81819eb0 firmware: restructure to avoid #[path = "..."] mod ...; 
Such code is fragile, introduces mess in dependencies, and
inflates compile times.
 2017-02-25 17:54:14 +00:00
whitequark d04e611232 firmware, compiler: rename rpc functions to be more consistent. 2017-02-25 14:12:58 +00:00
Sebastien Bourdeauducq e82ce3ea28 coredevice: ignore .dirty in version checks correctly 2017-02-25 20:05:05 +08:00
Sebastien Bourdeauducq 98be556143 drtioaux: fix compiler warnings 2017-02-25 12:18:57 +08:00
Sebastien Bourdeauducq f017d1771f gateware: remove unused configs in targets (not needed with new moninj) 2017-02-25 12:14:56 +08:00
Sebastien Bourdeauducq 5a16660aa2 runtime: new moninj protocol, TCP-based, with DRTIO support 2017-02-25 12:07:00 +08:00
Sebastien Bourdeauducq 1486a945d9 manual: update moninj network info 2017-02-25 12:06:35 +08:00
Sebastien Bourdeauducq 7d568b4bac style 2017-02-25 12:06:12 +08:00
whitequark 13c6e96760 firmware: implement dyld::Library::rebind. 2017-02-25 00:10:40 +00:00
whitequark 04ad267055 firmware: rewrite the dynamic linker in Rust. 2017-02-24 18:57:29 +00:00
Sebastien Bourdeauducq 360be0098f drtio: map local RTIO core on lower channels 2017-02-24 18:15:27 +08:00
whitequark 907589fb58 satman: simplify Makefile. 2017-02-23 10:29:25 +00:00
whitequark 623a605d3b satman: refactor type conversions. 2017-02-23 08:59:27 +00:00
Sebastien Bourdeauducq b34c6ba6b9 satman: process moninj packets 2017-02-23 16:24:05 +08:00
Sebastien Bourdeauducq 45ac0dcf57 drtioaux: add moninj packets 2017-02-23 16:23:51 +08:00
Sebastien Bourdeauducq 016743f079 libdrtioaux: do not attempt to access non-existent DRTIO gateware 2017-02-22 16:45:02 +08:00
Sebastien Bourdeauducq 257527629a firmware: use aux ping to determine when DRTIO satellite is ready 2017-02-22 15:26:32 +08:00
Sebastien Bourdeauducq a8ea557406 firmware: add DRTIO aux packet library (WIP) 2017-02-21 21:55:36 +08:00
Sebastien Bourdeauducq b455ea447d gateware: add moninj to drtio targets 2017-02-21 21:54:47 +08:00
whitequark a12876b239 firmware: update Cargo.lock. 2017-02-21 05:28:48 +00:00
whitequark 1dabe05c5a artiq_devtool: add clean command and --config option. 2017-02-21 05:28:19 +00:00
whitequark b468959e14 doc: manual/developing: update binutils patch URL. 2017-02-21 05:28:19 +00:00
Sebastien Bourdeauducq c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
Sebastien Bourdeauducq 8da28177a4 conda: bump migen 2017-02-20 15:52:05 +08:00
Robert Jördens e323e37829 pcu: refactor into a device 2017-02-19 19:34:55 +01:00
Robert Jördens b05d1bb7e3 coreanalyzer: fix corner case crash 2017-02-19 19:28:13 +01:00
Robert Jördens 1573ff5fc1 coreanalyzer: add WB stb signal 2017-02-18 14:53:10 +01:00
Robert Jördens 039ced6637 coreanalyzer: use VCD scopes for DDS/SPI 2017-02-18 14:25:01 +01:00
Robert Jördens 7519408857 coreanalyzer: add SPIMaster support 2017-02-18 14:13:20 +01:00
Robert Jördens 41e8acf3ad coreanalyzer handle input events without timestamp 
Offset the timeline by the first non-zero timestamp.
 2017-02-18 14:12:02 +01:00
Robert Jördens bc3fc26e34 coredevice: expose PCU 2017-02-18 14:09:12 +01:00
Robert Jördens 3e2dad6573 misoc: bump (mor1kx pcu) 2017-02-18 14:09:12 +01:00
Robert Jördens 6b5b679659 libboard: PCU regs 2017-02-18 14:09:12 +01:00
Robert Jördens c022b53578 kernel_cpu: enable perf counters 2017-02-18 14:09:12 +01:00
Sebastien Bourdeauducq 9501d37378 firmware: wait longer for Si5324 lock + more monitoring 2017-02-18 17:24:46 +08:00
Sebastien Bourdeauducq 7e8348a73e si5324: fix error handling 2017-02-18 14:12:18 +08:00
Sebastien Bourdeauducq 59e79673f7 satman: program Si5324 BWSEL depending on frequency 2017-02-18 14:12:01 +08:00
Sebastien Bourdeauducq 0bfce37fae satman: do not use Si5324 automatic clock switching 
The Si5324 is easily confused by the broken clock generated during link
initialization with BruteforceClockAligner. This commit prevents this problem.
 2017-02-18 13:32:40 +08:00
Sebastien Bourdeauducq bd55436668 protocols: increase asyncio line limit. Closes #671 2017-02-17 20:46:23 +08:00